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Hybrid sensor work for ILC

Hybrid sensor work for ILC

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Hybrid sensor work for ILC

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  1. Hybrid sensor work for ILC LCUK, Birmingham 18/11/13

  2. Report Kick-off meeting 1/11/13 Present in the meeting: Edinburgh (Victoria Martin), Glasgow (Craig Buttar, Richard Bates, Aidan Robson), Lancaster (Harald Fox), Liverpool (JoostVossebeld, Ashley Greenall, Tony Affolder). Institutes presented briefly on their expertise and infrastructure, the projects they are involved with, etc. Jointly a very strong expertise and infrastructure for silicon detector development is available. Institutes are heavily involved with ATLAS strip and pixel upgrades, LHC-b VeLo upgrade, HV-CMOS work for ATLAS, ... There is also PRD funding for generic work on HV-CMOS/hybrid technologies in Glasgow and Liverpool The meeting focussed on the option of developing a hybrid detector based on an HV-CMOS sensor.

  3. HV-CMOS/Hybrid sensors for ILC HV-CMOS: CMOS (deep N-well) implementation in high resistivity substrate • industry-standard process • wafer cost ~40% of planar sensors • small pixels with incorporated analogue/digital electronics • depleted region, charge collection through drift (rather than diffusion) • improved radiation tolerance (trapping losses) and timing performance • Example possible HV-CMOS detector for ILC • Hybrid pixel sensors, 4-side buttable device for vertex detector or pixel tracker • Hybrid strip or strixels for tracker, HV-CMOS sensor with strip or pixel ROIC. (Similar concept to SID Silicon tracker but implemented in CMOS)

  4. 2 funded PRD bids for HV-CMOS work Goals Glasgow PRD bid: • Basic understanding of charge collection inside the HVCMOS cell • Radiation hardness of HVCMOS • Document operational scenarios for HVCMOS (annealing and operation temperature) • Capacitively coupled pixel module development • TSV incorporation into the ROIC/HVCMOS to make 4 side-buttable device Goals Liverpool PRD bid (co-investigators Manchester and Imperial College) • Demonstrate use of a “pitch adaptor” in metal layers in CMOS to adapt sensor to footprint of different ROIC (FEI4, CBC2, TimePix) • Decouple sensor and ROIC geometry (towards larger area sensors) • Try different pixel, strixel, strip geometries in sensor • Use of ROIC with TSVs • Radiation hardness of HVCMOS This work is targeted at applications in future experiments, with a primary focus probably on the HL-LHC, but there is scope to test ILC specific solutions and significant synergy.

  5. Synergy / scope for collaboration • Edinburgh, Glasgow, Lancaster, Liverpool: wide range of expertise and infrastructure for Silicon detector development. • ATLAS: HV-CMOS task force to study feasibility of an application at HL-LHC time-scale. • HV-CMOS collaboration: hybrid HV-CMOS pixel sensors with a FE-I4 family ROIC (also tested TimePix) and strip HV-CMOS with ABCN ROIC Includes: Heidelberg (sensor design), Geneva, CERN, CPPM, Bonn, LBNL, Glasgow • LHC-b VeLo: hybrid pixel sensors with VeloPix(MediPixfamily) • CERN thinned hybrid pixel sensors with CLICPix(MediPixfamily) programme. Currently using Liverpool designed planar pixel sensor. • To investigate: any scope for collaboration with US groups on SID Silicon tracker?

  6. Possible UK contributions Pixel sensors for vertex detector or pixel tracker Power consumption: test HV-CMOS in power pulse mode (joint effort with DAQ?) Material budget: will need thinning and assembly studies Resolution: Underlying HV-CMOS pixel size is 2.5x2.5 m2 ,but these are ganged together. Some level of position encoding is possible! Can demonstrate in collaboration with CLICPix Timing performance: what is achievable Efficiency: what can be achieve with 4-side buttable devices Technical contributions (for example in collaboration with CLICPix) • Precision placement • Thinning and related assembly issue Strip, strixel sensors for tracker (less to more speculative approaches) Hybrid HV-CMOS sensors with 2D readout, using position encoding on the strip. Still aimed at strip ROIC (could remove need for stereo layers) Strip or strixel sensor read out with a pixel RIOC • 4-side buttable device or multiple reticules in a single device (1 ROIC to serve 2 or 4 sensors reticules). This needs ROIC with TSVs • Full wafer size device. Needs stitching

  7. Consider various funding* scenarios *capital cost + new posts + CG non-core effort (travel costs not included) Indication of what UK could contribute at different funding levels 25k£/yr – 50k£/yr Modest contributions to work done elsewhere and generic R&D • Contribution to MPW runs and wafer processing • Minor FTE fractions of engineering time • Flex circuits for testing, PCB’s for DAQ (overlap with DAQ) 100k£/yr - 250k£/yr • TSV work (if needed) • Contribution to engineering run (full cost ~180kEURO) • More substantial fraction of for example an electronic design engineer for dedicated prototyping

  8. Homework We will start by capturing in detail ILC constraints for vertex detector and tracker. • Granularity (resolution and occupancy) • Timing resolution and/or readout speed • Material budget • Power and cooling constraints (details of pulse mode operation) • Geometry, mechanical, ..


  10. ILD Silicon tracker • Vertex detector and a large TPC. • Silicon strip detectors inside (SIT, FTD) and behind the TPC (SET, ETD) • double (stereo) layers of planar Silicon • In forward region double-sided planar Si considered • 200 um thick, “edgeless” sensors to avoid need for overlapping sensors • integrated pitch adapters for direct bonding to SiTRK ASIC (8 bit digital) • Bump-bonding or alternative3D interconnects to be considered

  11. SID Silicon tracker • Silicon strip detectors on barrels and disks surrounding the VXD Sensor technology / module proposal • Planar silicon • 5 Barrels: default single layer axial only strips • 4 Disks: double stereo layers of planar Si • Double metal layers • routing to bump-bonding pad array to KPIX ASIC and • power and signal lines between (bump-bonded) readout cable and KPIXASIC • In forward region double-sided planar Si considered