1. PCI Express Switch Yearly Project

2. HS/DSL Project Midterm Presentation Implementation and Synthesis of a 3-Port PCI-Express Switch Supervisor: Mony Orbach Yael Grossman Arik Krantz

3. Project Specifications We will implement: • 3 - port switch for PCI-Express • 1 upstream, 2 downstream full-duplex ports • Up to 2.5 Gbit/sec transfer rate • CRC support at the DLL layer • Independent packet handling per port • Packet routing between ports through lookup tables

4. Local/Global Mechanisms • Send Queue 1 and 2 (SQ1, SQ2) Contain packets routed to current port from the other two switch ports. We have one buffer for each queue in order to prevent simultaneous memory write. • ACK/NACK Queue (ACKQ) Used to store DLLPs for each received TLP while they await sending. • Replay Buffer (RB) Contains all the packets that have been sent on the outgoing queue and have not yet received an ACK. • Send/Receive Pipelines Includes logic for incoming and outgoing packets. • Routing Mechanism Includes an independent copy of the routing table. Local • Packet Storage in Common Memory Space Enables fast packet forwarding between ports • Global Initialization at Boot Time Initialize routing tables with system layout. Global

5. Receive Flow • This mechanism is applied per port. • It displays the sequence of actions that the switch executes on a received packet. • Packet is received on incoming lane • Packet type is determined and CRC check is performed • According to packet type (DLLP or TLP), we take appropriate action.

6. Route packet and Enqueue (TLPs) ACK/ NACK Send Logic (TLPs) CRC Logic Block Replay Buffer Logic (DLLPs) Continue

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11. Send Flow • This mechanism is applied per port. • It displays the sequence of actions that the switch executes in order to send a packet on the outgoing lane. • The switch contains 4 buffers with packets to be sent: SQ1, SQ2, ACKQ and the Replay Buffer. • It will decide from which buffer to select the packet to be sent (if they aren’t empty), and send it on the outgoing lane.

13. Completed Tasks Detailed design • Data flow diagram (transmitter/ receiver) for ports • Queue and buffer structure for ports • Packet handling algorithms System block design • Completed most of higher-level block design • Work in progress on lower-level blocks Preparation for VHDL coding • Learned to work with HDL designer • Learned VHDL (basic level)

14. Semester Plan Complete design for all sub-blocks 3 weeks • Routing/lookup table mechanism • Arbitration logic • Send Queue implementation • Concurrency issues in queue access • Deal with unresolved issues such as: - Interaction with Physical Layer - Understand memory segmentation VHDL design1 week • Division of the system into interconnected entities • Definition of appropriate architecture per entity • Preparation for VHDL implementation Exam period break… 4 weeks VHDL design1 week • …continue design (and start coding).

15. Thank You!