1 / 92

Introduction to Xilinx CPLDs

Introduction to Xilinx CPLDs. Agenda. CPLD Introduction XC9500 Family Overview CoolRunner XPLA3 Overview CoolRunner-II Overview IQ Products for Automotive and Industrial Software Updates and Online Support Customer Success Stories. C omplex P rogrammable L ogic D evice. interconnect.

keefer
Télécharger la présentation

Introduction to Xilinx CPLDs

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Introduction to Xilinx CPLDs

  2. Agenda • CPLD Introduction • XC9500 Family Overview • CoolRunner XPLA3 Overview • CoolRunner-II Overview • IQ Products for Automotive and Industrial • Software Updates and Online Support • Customer Success Stories

  3. Complex Programmable Logic Device interconnect macrocells macrocells A hybrid of PLD blocks & interconnect for mid-size logic designs

  4. Schematic Capture Simulation Synthesis 0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1 Timing Analyzer Back-Annotation CPLD Design Flow Specification libraries HDL Gates of the design ... netlist CPLD Design Flow Verification test vectors Implementation Translate Fitting ... are “fitted” to the CPLD Download/ Program device System Debug printed circuitboard

  5. CPLD TPD (ns) High Performance • Maximum registered frequency • Fastest operation of flip-flops (MHz) • Pin-to-Pin combinatorial delay • Time from input, thru interconnect to output (ns) CPLD Macrocell fMAX (MHz)

  6. CPLD CPLD Wide Package Offering • High pin count package for lots of I/Os • Maximum logic with minimal I/Os • Logic consolidation for space (vs. discrete devices) • Lower cost packaging A smaller CPLD package means a smaller board!

  7. CPLD 3.3/2.5/1.8v CPLD Voltage Integration 5v, 3.3v, 2.5v, 1.8v and 1.5v • 3.3v & 2.5v is the current market trend moving to 1.8v and below for portable and low power applications • Cost reduction to eliminate 5v supply and regulators with 5v tolerance • Some components will not migrate to 3.3v or below • Need to interface with 3.3v, 2.5V, 1,8v and/or 1.5v components 5v* 5v* 5v* 5v* 5v* 3.3v* 1.5v* 1.8v* 2.5v* * 3.3v CPLD required to interface with 5v, 3.3v & 2.5v components * 2.5v CPLD required to interface with 3.3v, 2.5v & 1.8v components *1.8v CPLD required to interface with 3.3v, 2.5v, 1,8v & 1.5v components

  8. System Integration Advantage

  9. System Level Savings • High volume economies of scale • Single chip for multiple system solutions • Increase volume means reduction in all related costs • Reference designs • Minimize risk and shorten design cycle • Lowest cost per I/O • Examples include • On The Fly (OTF) reconfiguration • Two devices for the price of one

  10. Designers Need Low Power • Longer lasting battery life • Lower overall system cost (eliminate fans/ reduce power supplies) • Increased system reliability • Fits into hand-held applications

  11. High Speed CMOS Logic 74HC373 74HC373 74HC373 74HC137 SOL 24 74HC137 74HC374 74HC374 74HC374 74HC137 TSSOP 24 74HC157 74HC157 74HC00 74HC00 74HC20 74HC20 74HC21 74HC21 74HC138 74HC138 74HC138 SOL 24 CPLD Advantage over Discrete Logic XPLATM Architecture Equivalent to TQFP 100 XCR3128XL Or XCR3064 XL 3.3V parts in the same package bridging two densities for added design flexibility Real design example: Aircraft Passenger Handset - Smaller PCB with less layers (lower cost) - 7 to 3 layers! - One part to purchase & stock, less inventory - One part to pick and place in manufacture, saving time - Design can be changed and enhanced without PCB re-layout - even in the field - Stock and purchase one part instead of 17 in this example!

  12. Xilinx CPLDHigh Volume Shipments Units Shipped • Xilinx currently ships >10M CPLD units per Qtr • WW CPLD market share growing at >1% per Qtr

  13. CPLD Product Portfolio • 3.3V core • 2.7V - 5V I/O • LVCMOS, LVTTL • Low power • Fast Zero Power • 1.8V RealDigital core • 1.5V - 3.3V I/O • SSTL, HSTL, LVCMOS, LVTTL • Lower power • DataGATE • Clocking features • Clock Divide • CoolCLOCK • DualEDGE • I/O banking • 2.5V core • 1.8V - 3.3V I/O • LVCMOS, LVTTL • I/O banking • 3.3V core • 2.5V - 5.0V I/O • LVCMOS, LVTTL

  14. Quick Design Capability with CPLDs

  15. Product Lifetime Dynamics Units Cellular Target high volume, short production life applications PDA PC Games TV 1 2 Years in Production New products stay in volume for shorter periods, Time To Market is critical!

  16. ASIC Development Take Too Long! • Product life cycles maybe shorter than ASIC development time • Multiple ASIC spins may miss the market window • Smaller than expected run rates may not justify the ASIC development cost • Long ASIC development times do not allow last minute design revision changes • Revisions leave little time to run in production • Programmable logic allow customers to address market changes quicker

  17. ASICs Give Designers Only ONE Chance Freeze design here No chance for last minute design changes ASIC Spec Design & Verification System Integration Silicon Prototype Silicon Production First Ship Re-programming allows last minute design changes CPLD Spec System Integration Design & Verification First Ship Freeze design here • CPLD flexibility allow performance analysis and late HW/SW changes meeting customer needs and improves Time To Market with faster, lower risk designs

  18. CoolRunner Reference Designs • Shorten design cycle time • Eliminate code porting costs for next design cycle • Re-use of HDL is reliable and stable • Minimize design risk by using reference designs • Availability of reference designs prepares you for unexpected system changes • Update main processor but it does not incorporate correct bus interface • Further improve customer’s Time To Market • Proven designs for quick turn requirements

  19. Faster Designs with FREECoolRunner Reference Designs Coming soon Free VHDL design code: www.xilinx.com/products/xaw/coolvhdlq.htm

  20. CoolRunner-II Design Kit

  21. Development Board & Cable Support Note: There may be regional variations because of different mains voltages - check locally for full part number

  22. CPLD Software Improvements in 6.1 • Ease of use • Improved CPLD process flow • Single process (Implement Design) will pull the design through the entire fitting process • Granular control still possible for power users by expanding individual processes • New design creation aids • New project wizard leads the user through the project creation process • Add existing source / Create new source processes - assist in getting started faster • Centralized process properties menu • Web Update • Built in utility checks for service packs and supplemental CPLD updates • Downloads and installs update in single step XC9500XL / XV Product Overview File Number Here

  23. Non-Volatile Xilinx CPLD Process Leadership Year used in Year used in SPLD/CPLD Technology Memories SPLD/CPLD Pioneer Bipolar Fuse 1973 1978 MMI (AMD) EPROM 1979 1984 Altera EP-series 5V EEPROM 1986 1991 Lattice ispLSI 5V FLASH 1990 1995 Xilinx XC9500 3.3V FLASH 1993 1998 Xilinx XC9500XL 2.5V FLASH 1996 2000 Xilinx XC9500XV

  24. Higher Voltage CPLD Solutions To Fit Every Need • 5 / 3.3 / 2.5V core • 36-288 macrocells • High Performance • Superior pin-locking • Low cost XC9500 Families XC9500 XC9500XL XC9500XV 2.5V core 5V core 3.3V core

  25. XC9500/XL/XV Family FeaturesOverview • High fMAX = 278 MHz • Fast TPD= 3.5nS • Instant productivity software tools • Best pin-locking capability • Best ISP/JTAG support • Support for all ATE manufacturers • Advanced packaging including CSP • XC9500XL for 3.3v (5v tolerant & 2.5v I/O) • XCR9500XV for 2.5v (1.8v & 3.3v I/O) • Best CPLD pricing in the industry! CPLD Designer Needs High Performance Time to Market Fit in Existing Flow Package offering 5v,3.3v & 2.5v Lowest cost

  26. 3.3v ISP XC9536XL XC9572XL XC95144XL XC95288XL 2.5v ISP XC9536XV XC9572XV XC95144XV XC95288XV Macrocells 36 72 144 288 Usable Gates 800 1600 3200 6400 t ( ns) XC9500XL 5 5 5 7.5 pd t ( ns) XC9500XV 4 5 5 6 pd Registers 36 72 144 288 f XC9500XL 178 178 178 125 SYSTEM XC9500XV 200 178 178 151 Packages PC44 PC44 CS48 CS48 VQ44* VQ44* VQ64 VQ64 TQ100 TQ100 TQ144 TQ144 CS144 PQ208 BG256 FG256* CS280* XC9500XL / XV Families

  27. XC9500 5V Family XC9536 XC9572 XC95108 XC95144 XC95216 XC95288 36 72 108 144 Macrocells 216 288 Usable Gates 800 1600 2400 3200 6400 4800 5 7.5 7.5 7.5 15 tPD (ns) 10 36 72 108 144 288 Registers 216 Max. User I/Os 34 72 108 133 192 166 44VQ 44PC 48CSP 44PC 84PC 100TQ 100PQ 84PC 100TQ 100PQ 160PQ 100TQ 100PQ 160PQ Packages 208HQ 352BG 160PQ 208HQ 352BG

  28. XC9500 5V Family XC9536 XC9572 XC95108 XC95144 XC95216 XC95288 36 72 108 144 Macrocells 216 288 Usable Gates 4800 800 1600 2400 3200 6400 10 5 7.5 7.5 7.5 15 TPD (ns) 36 72 108 144 216 288 Registers Max. User I/Os 34 72 108 133 192 166 44VQ 44PC 48CS 44PC 84PC 100TQ 100PQ 84PC 100TQ 100PQ 160PQ 100TQ 100PQ 160PQ Packages 208HQ 352BG 160PQ 208HQ 352BG

  29. XC9500XL 3.3V Family XC9536XL XC9572XL XC95144XL XC95288XL 36 72 144 Macrocells 288 Usable Gates 800 1600 3200 6400 tPD (ns) 5 5 5 6 Registers 36 72 144 288 Max. User I/Os 36 72 117 192 PC44 VQ44 CS48 VQ64 PC44 VQ44 CS48 VQ64 TQ100 TQ100 CS144 TQ144 TQ144 PQ208 BG256 FG256 CS280 Packages

  30. XC9500XV 2.5V Family XC9536XV XC9572XV XC95144XV XC95288XV 36 72 144 Macrocells 288 Usable Gates 800 1600 3200 6400 tPD (ns) 5 5 5 6 Registers 36 72 144 288 Max. User I/Os 36 72 117 192 PC44 VQ44 CS48 PC44 VQ44 CS48 TQ100 TQ100 CS144 TQ144 TQ144 PQ208 FG256 CS280 Packages

  31. CPLD CPLD XC9500/XL/XV Family Features Driving the ISP Revolution • Complete support of ISP designer’s Product Life Cycle • Provides industry’s best pin-locking CPLD at lowest price • Complete “state-of-the-art” software support • CPLDs key part of the Xilinx “total logic solution” • Benefits of ISP: • No need for costly device programmers, fewer board re-spins, less scrap and re-work, reduces design and development time scales, enables field upgrades, eliminates unnecessary package handling, x Program the whole board not each chip!

  32. XC9500/XL/XV FamilyFeatures Most Complete JTAG Testability • IEEE Std 1149.1 boundary-scan • Testability & advanced system debug/diagnosis • 8 instructions supported (incl. CLAMP) • Full support on all family members • 1532 Industry-standard ISP interface • Complete 3rd party support • Benefits of JTAG:Improved testability, higher system reliability, cheaper test equipment, shorter test time, reduced spare board inventories, reduces device handling.

  33. XC9500/XL/XV Family Features Innovative CSP Packaging • New 48-pin Chip Scale Package (CSP) • 1/3 size VQFP-44, 82% smaller than PLCC-44 • Big board space benefits • New 144-pin CSP (117 user I/Os) • Uses standard IR surface mounting process • Supports industry’s high growth market segments • Communications, Computers, Consumer PC44 5.6X

  34. XC9500/XL/XV Family FeaturesNew price points open upnew apps • Motherboards for PCs and servers • PC peripherals and add-on cards • DVD players/controller cards • Graphics cards • Automotive • Engine control • Automotive navigation systems (GPS) • Consumer • LAN / DSLAM • Video Games/Toys

  35. CPLD Software Improvements in 6.1 • Ease of use • Improved CPLD process flow • Single process (Implement Design) will pull the design through the entire fitting process • Granular control still possible for power users by expanding individual processes • New design creation aids • New project wizard leads the user through the project creation process • Add existing source / Create new source processes - assist in getting started faster • Centralized process properties menu • Web Update • Built in utility checks for service packs and supplemental CPLD updates • Downloads and installs update in single step CoolRunner XPLA3 Product Overview File Number Here

  36. XCR3000XL Family FeaturesOverview CPLD Designer Needs • High fMAX = 200MHz • Fast TPD = 5nS • Instant productivity software tools • Best ISP/JTAG support • World’s Smallest BGAs (CP56) • Industry’s 1st & most efficient architecture - PLA • Ultra low power operation • No power/performance tradeoffs • Low Power = High Reliability High Performance Time to Market Package offering Low power THESE PARTS ARE FOR LOW POWER APPLICATIONS!

  37. CoolRunner XPLA3 Family

  38. 200 180 CY37128 160 M4A3 140 M4LV 120 100 7000A 80 3000A 60 ISPLSI2128VE 40 XC95144XL 20 XCR3128XL 0 Hours of operation XCR3000XL Family Features Low Power • Dynamic Battery Life • Populated with 16 bit counters @ 20MHz • 2 AA batteries • Non CoolRunner devices in low power mode Competitive Device Families 3.3V CPLD Low Power Leadership!

  39. XCR3000XL Family Features Extra ‘Hidden’ Benefits of Low Power • Eliminates Expensive Heat Sinks & Cooling Fans • Heat Sinks: $ 0.50 - $ 12.00 • Fans: $ 3.50 and up • Decreases Power supply component size for: • High Performance • Small Portable Form Factors • Computing Lap & Palm Enclosures • Higher product density Less Heat = Higher Performance, Cost Savings & Reliability!

  40. Ambient Xilinx XCR3256XL-7TC144 Cypress CY37256VP160-100AC Lattice M4LV-128/64-10YC Altera EPM7256AETC144-7 Altera EPM3256ATC144-7 25 30 35 40 45 50 55 60 Lattice ispLSI2192VE-100LT128 Degrees Centigrade Thermal Emissions Comparison • Devices programmed with 16 bit counters with the MSB brought out to an LED and operated at 50MHz • Where applicable, competitive devices were in non-turbo mode • Note the MACH4 device is 128 macrocells, Lattice is 192 macrocells (largest in the family)

  41. Altera 3K Test IR00004.ISI Thermal Characteristics The Altera MAX3000A 256 macrocell device was powered up in low power mode and loaded with a 16 bit counter and clocked at 50MHz. A thermal imaging camera measured the Altera device (P1) to be @ 40.23ºC, (P2) was a CoolRunner XCR3256XL device @ 30.03ºC, the back ground temperature was 22.88ºC (P3)

  42. Infant Mortality Constant Failure Wear out FITS Temperature Time Higher System Reliability • Activation Energy EA Aggravated by Temperature! • Increased Temperature = Decreased Reliability

  43. XPLA3 supports small industry standard packages New Chip Scale Packaging CS48 CP56 17.6 mm 44 PLCC 12 mm 44 VQ 17.6 mm 7 mm 48 CS 12 mm 56 CP 7 mm 6 mm 6 mm Lower Power = Smaller Packages

  44. The RealDigital CPLD A New Class of CPLD with High Performance and Ultra Low Power without Compromise!

  45. 0.60µ 5.0 Volt Devices 0.50µ High speed and low power barrier 3.3 Volt Devices 0.35µ 2.5 Volt Devices 0.25µ CR-II FZP 1.8 Volt, 0.18µ Devices 0.18µ Sense amps don’t scale well CPLD Sense amp Designs Have Migration Limits Sense amp based CPLD technologies don’t scale effectively beyond 0.18µ

  46. Clock and Control Signals Function Block 1 Function Block n MC1 MC1 16 FB 16 FB I/O MC2 MC2 I/O I/O I/O PLA PLA 16 16 I/O Blocks I/O Blocks AIM 40 40 I/O I/O MC16 MC16 16 16 Fast Inputs Fast Inputs High Level Architecture

  47. 40 From AIM MC 1 Feedback to AIM PLA Array 40x56 To I/O Block 16 56 Product Terms MC 16 3 Global Clocks Global Set/Reset Function Block Architecture

  48. C A B X Y Indicates ‘used’ junction Indicates ‘unused’ junction Indicates ‘fixed’ junction Logic Allocation Advantage PAL: Requires 4 product terms! PLA: Requires only 3 product terms! C A B Can NOT share common logic X = A & B # C Y = A & B # !C Y X Common logic may be shared in CoolRunner-II

  49. PTA CTS GSR GND to I/O PTA CTR GSR GND Macrocell Architecture FB Inputsfrom AIM application notes: http://www.xilinx.com/apps/epld.htm 40 PLA Array 49 P terms Macrocell 4 Control Terms from I/O Block (Fast Input) Feedback to AIM PTA PTB VCC PTC GND S Q D/T FIF Latch DualEDGE CE PTC GCK0 GCK1 CK R GCK2 CTC PTC

  50. Weak Pullup/Bus Hold I/O Pin I/O Pin I/O Block Characteristics VREF for Local Bank HSTL & SSTL VCCIO VREF to AIM 128 macrocell and larger devices Input Hysteresis to Macrocell (Fast Input) 3.3V - 1.5V Input Slewrate VCCIO from Macrocell Enabled Control Term PTB / 4 GTS[0:3] CGND Open Drain Disabled

More Related