1 / 54

ECE 551: Digital System * Design & Synthesis

ECE 551: Digital System * Design & Synthesis. Lecture Set 2 2.1: Verilog – The Basics 2.2: Verilog – Simulation and Testbenches. ECE 551 - Digital System Design & Synthesis Lecture 2.1 – Verilog – The Basics. Overview. Modules. Primitives.

kevinn
Télécharger la présentation

ECE 551: Digital System * Design & Synthesis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ECE 551: Digital System * Design & Synthesis Lecture Set 2 2.1: Verilog – The Basics 2.2: Verilog – Simulation and Testbenches

  2. ECE 551 - Digital System Design & SynthesisLecture 2.1 – Verilog – The Basics • Overview • Modules • Primitives • Styles • Structural Descriptions • Language Conventions • Number Representation ECE 551 Spring 2003

  3. Modules • The Module Concept • Basic design unit • Modules are: • Declared - • define the module and what it does • includes both interface & implementation • Instantiated • Use the module in another design or testbench • Note: Module declarations cannot be nested ECE 551 Spring 2003

  4. Module Declaration * module decoder_2_to_4 (A, D) ; input [1:0] A ; output [3:0] D ; // RTL Description assign D = (A == 2'b00) ? 4'b0001 : (A == 2'b01) ? 4'b0010 : (A == 2'b10) ? 4'b0100 : (A == 2'b11) ? 4'b1000 : 4'bxxxx) ; endmodule Decoder 2-to-4 4 2 A[1:0] D[3:0] ECE 551 Spring 2003

  5. Bachus-Naur Form • Verilog syntax conforms to the Bachus-Naur Form (see Text Appendix ? And IEEE 1364-2001 Annex ??) • Name ::= begins a definition • | introduces an alternative (or) • bold text correspond to Verilog key words • [item] an optional item that may appear once • {item} an option item that may appear more than once |... Other alternatives exist, but not listed ECE 551 Spring 2003

  6. Module Declaration Syntax module_declaration ::= module_keyword module_identifier [list of ports]; {module_item} endmodule module_keyword ::= module|macromodule list_of_ports ::= (port {, port}) module_item::= module_item_declaration | parameter_override | continuous_assign | gate_instantiation | udp_instantiation | module_instantiation | specify_block | initial_construct | always_construct ECE 551 Spring 2003

  7. Module Declaration - * Annotated module decoder_2_to_4 (A, D) ; /* module_keyword module_identifier (list of ports) */ input [1:0] A ; // input_declaration output [3:0] D ; // output_declaration // RTL description assign D = (A == 2'b00) ? 4'b0001 : (A == 2'b01) ? 4'b0010 : (A == 2'b10) ? 4'b0100 : (A == 2'b11) ? 4'b1000 : 4'bxxxx) ; /* continuous_assign- ment */ endmodule ECE 551 Spring 2003

  8. Module Declaration– Verilog 2001 • Example module half_adder (input wire [1:0] x, output reg [1:0] z); //ANSI style: I/O & datatype declarations in module ports // behavioral description always@(x) begin z[1] <= x[1] ^ x[0]; // x1 XOR x0 z[0] <= x[1] & x[0]; // x1 AND x0 end endmodule • Works in Modelsim ECE 551 Spring 2003

  9. Module Identifiers and Ports • Module identifiers - must not be keywords! • Ports • First example of signals • Scalar: e. g., c_out • Vector: e. g., A[1:0], A[0:1], D[3:0], and D[0:3] • Range is MSB to LSB (left to right) • Can refer to partial ranges - D[2:1] • Type: defined by keywords • input • output • inout (bi-directional) ECE 551 Spring 2003

  10. Module Instantiation Syntax module _instantiation ::= module_identifier [parameter_value_assignment] module_instance {, module_instance}; parameter_value_assignment ::= # (expression {, expression}) module_instance ::= name_of_instance ([list_of_module_connections]) name_of_instance ::= module_instance_identifier [range] list of module connections ::= ordered_port_connection {, ordered_port_connection} | named_port_connection {, named_port_connection} ordered_port_connection ::= [expression] named_port_connection ::= . port_identifier ([expression]) • Example: full_add #4FA[3:0](A, B, C, Sum, C_out); • All modules instantiated in one statement must have same delay. ECE 551 Spring 2003

  11. Module Instantiation Example module decoder_3_to_8 (A, D) ; input [2:0] A ; output [7:0] D ; wire [7:0] D_temp; wire A2_bar; not N0 (A2_bar, A[2]); // primitive instant. decoder_2_to_4 D0 (A[1:0], D_temp[3:0]);// module instant. decoder_2_to_4 D1 (A[1:0], D_temp[7:4]);// module instant. and [3:0] (D[3:0], D_temp[3:0], {4 {A2_bar}}); and [3:0] (D[7:4], D_temp[7:4], {4{A[2]}}); endmodule Decoder 3-to-8 8 3 A[2:0] D[7:0] ECE 551 Spring 2003

  12. Module Instantiation Examples • Single module instantiation for two module instances decoder_2_4 D0 (A[1:0], D_temp[3:0]), D1 (A[1:0], D_temp[7:4]); • Single module instantiation for array of instances half_add [3:0] (sum[3:0], c_out[3:0], A[3:0], B[3:0]); • Named port connections decoder_2_4 D0 (.D (D_temp[3:0]), .A (A[1:0])); • ports no longer have to be in order • more likely to get ports correct ECE 551 Spring 2003

  13. Primitives • Predefined Primitives • Built into Verilog • Basic combinational and switch-level building blocks for structural descriptions. For example, nand(c, a, b) // Output must be first • Have behavior, but no lower-level description • User-Defined Primitives • Basic combinational and sequential structural building blocks • Have behavior based on lower-level descriptions using truth tables • Covered in detail later ECE 551 Spring 2003

  14. Built-in Primitives • Combination logic primitives • and, nand, or, nor, xor, xnor (one output, multiple inputs) and(z, a[7:0]); • buf , not (multiple outputs, one input) not(a_not[7:0], a); • Three state logic primitives • bufif0, bufif1, notif0, notif1 (multiple outputs, one input, one enable) bufif1(a_buf[7:0], a, enable); • Switch level primitives • MOS gates, CMOS gates, Bi-directionals , Pull Gates • Useful when doing transistor-level design and simulation • Not used in this course • See Appendix A for details ECE 551 Spring 2003

  15. Built-in Primitives • No declarations - can only be instantiated • All output ports appear in list before any input ports • Optionally specify: instance name and/or delay and N25 (Z, A, B, C); // name specified and #10 (Z, A, B, X), (X, C, D, E); // delay specified and #10 N30 (Z, A, B, D); // name and delay specified /*Usually better to provide instance name for debugging.*/ or N30 (Out1, A1, A2, A3), // 3-input OR N41 (Out2, B1, B2);// 2-input OR ECE 551 Spring 2003

  16. Structural Model Example module majority (V1, V2, V3, major) ; input V1, V2, V3 ; output major ; wire N1, N2, N3; and A0 (N1, V1, V2), A1 (N2, V2, V3), A2 (N3, V3, V1); or O0 (major, N1, N2, N3); endmodule N1 V1 and A0 V2 N2 V2 and A1 or O0 major V3 N3 V3 and A2 V1 ECE 551 Spring 2003

  17. Descriptive Styles • Structural - instantiation of primitives and modules • RTL/Dataflow - continuous assignments • Behavioral - procedural assignments ECE 551 Spring 2003

  18. Style Example - Structural * module full_add (A, B, CI, S, CO) ; input A, B, CI ; output S,CO ; wire N1, N2, N3; half_add HA1 (A, B, N1, N2), HA2 (N1, CI, S, N3); or G1 (CO, N3, N2); endmodule module half_add (X, Y, S, C); input X, Y ; output S, C ; xor (S, X, Y); and (C, X, Y); endmodule ECE 551 Spring 2003

  19. Style Example - RTL/Dataflow module full_add_rtl (A, B, CI, S, CO) ; input A, B, CI ; output S,CO ; assign S = A ^ B ^ CI; //continuous assignment assign CI = A & B | A & CI | B & CI; //continuous assignment endmodule ECE 551 Spring 2003

  20. Style Example - Behavioral module full_add_bhv (A, B, CI, S, CO) ; input A, B, CI ; output S,CO ; reg S, CO; /* variable required to “hold” values between events */ always@(A or B or CI) /*event list – change triggers execution */ begin S <= A ^ B ^ CI; // procedural assignment CO <= A & B | A & CI | B & CI; // procedural assignment end endmodule ECE 551 Spring 2003

  21. Connections • By position association • module decoder_2_4_with_enable (A, E_n, D); • decoder_2_4_with_enable DX (X[3:2], W_n, word); • A = X[3:2], E_n = W_n, D = word • By name association • module decoder_2_4_with_enable (A, E_n, D); • decoder_2_4_with_enable DX (.E_n(W_n), .A(X[3:2]), .D(word)); • A = X[3:2], E_n = W_n, D = word ECE 551 Spring 2003

  22. Empty Port Connections • Empty Port Connections • module decoder_2_4_with_enable (A, E_n, D); • decoder_2_4_with_enable DX (X[3:2], , word); E_n is at high-impedance state (z) • decoder_2_4_with_enable DX (X[3:2], W_n ,); Outputs D[3:0] unused. • General rules • empty input ports => high impedance state (z) • empty output ports => output not used ECE 551 Spring 2003

  23. Multiple Instantiations/Assignments • Instantiate multiple gates: nand #1 G1 (y1, a1, a2, a3), G2 (y2, a2, a3), G3 (y3, a1, a3); // same delay • Assign multiple values assign # 1 y1 = a1 ^ a2, y2 = a2 | a3, y3 = a1 & a3; ECE 551 Spring 2003

  24. Arrays of Instances - 1 module array_of_xor (y, a, b) input [3:0] a,b; output [3:0] y; xor [3:0] (y, a, b) // instantiates 4 XOR gates endmodule module array_of_flops (q, data_in, clk, set, rst) input [7:0] data_in; // one per flip-flop input clk, set, rst; // shared signals output [7:0] q; // one per flip-flop /* instantiate flip-flops to form an 8-bit register */ flip_flop M [7:0] (q, data_in, clk, set, rst) endmodule ECE 551 Spring 2003

  25. Arrays of Instances - 2 module add_array (A, B, CIN, S, COUT) ; input [3:0] A, B ; input CIN ; output [3:0] S ; output COUT ; wire [3:1] carry; /* Instantiate four full-adders to form a 4-bit ripple- carry adder */ full_add FA[3:0] (A,B,{carry, CIN},S,{COUT, carry}); endmodule ECE 551 Spring 2003

  26. Hierarchy • Established by instantiation of modules and primitives within modules • Typically use a top-down design methodology • Verify the design using bottom-up strategy • For example: Add_full Add_half or Add_half xor not nand ECE 551 Spring 2003

  27. Language Conventions • Verilog is case-sensitive • Don’t use the same name for different items in the same scope • All Verilog key words are lower case • Identifiers have upper case or lower case letters, decimal digits, and underscore • Specify “strings” in double quotes • // and /* comment */ are used for comments • Names beginning with $ denote built-in systems tasks for functions (e.g., $monitor) ECE 551 Spring 2003

  28. Representing Numbers • Numbers can be represented in: decimal (d or D), hex (h or H), octal (o or O), and binary (b or B) • Representation for numbers is <size>’<base_format><number> where size: gives size in bits (optional) – default at least 32 base_format: tells base (d, h, o, or b) – default decimal number: a value expressed in the specified base • Real numbers can use scientific notation (e.g., +1.02e-4) ECE 551 Spring 2003

  29. Examples of Representing * Numbers • Number Decimal Equivalent Stored 4’d3 3 0011 8’ha 10 00001010 8’o26 22 00010110 5’b111 7 00111 8’b0101_1101 93 01011101 8’bx1101 - xxxx1101 • Numbers whose most significant bit is x or z are extended with x or z. ECE 551 Spring 2003

  30. Things to Know • Module Syntax & Its Use • Combinational Logic Primitives & Their Use • Description Styles • Structural Description • Connections • Multiple Instances • Arrays • Continuous Assignment • Hierarchical Design • Language Conventions & Number Representation ECE 551 Spring 2003

  31. Lecture 2.2 - Simulation and Testbenches Overview • Simulation • Event-Driven Simulation • Simulation with Transport Delays • Simulation with Inertial Delays • Verilog Simulation Scheduling Semantics • Stimulus Generation & Response Monitoring • Generic Simulation Structure • Testbench Approach ECE 551 Spring 2003

  32. Verilog Simulation Signals • Values • {0, 1, x, z} • x - Unknown, ambiguous • z - High impedance, open circuit • Strengths • Signals have strength values for “switch level” simulation • Not used in this course ECE 551 Spring 2003

  33. Hypothetical Approach: Divide time into small increments and simulate all element outputs for each increment of time. Problem: Computationally very intensive and slow. Alternative Approach: Simulate an element only when its inputs have changed. Why effective? For any time increment, few signals are changing, so activity limited. Event-Driven Simulation ECE 551 Spring 2003

  34. Event-Driven Simulation • Formally, an event occurs when a signal changes in value. • Simulation is event-driven if new values are computed: • only for signals affected by events that have already occurred, • only at those times when changes can occur. ECE 551 Spring 2003

  35. Event-Driven Simulation • Operation of simulator depends on a time-ordered event queue. • Initial events on the list consist of input changes. These changes cause events to be scheduled (placed on the queue) for execution at a later time. • If the event queue becomes empty, all simulation activity ceases until another input change occurs. ECE 551 Spring 2003

  36. Event-Driven Simulation • Example: A Y X C Z B ECE 551 Spring 2003

  37. A Y X Z B C x x x x x x 1** 1** 1 1 0 0 1 0** 1 0 1 1 Event-Driven Simulation • Zero Delay Model ECE 551 Spring 2003

  38. Event-Driven Simulation • Unit Delay Model A Y X Z B C x x x x x x x x 1** 1** x x 1 1 0* x x x x 1 1* 1 0 1* 0* 1 1 1 0 1 0 1 1 0** 0 1 0 1 1 0 1* 1 0 1 0* 0 1 1 1* 1 0 0 1 1 ECE 551 Spring 2003

  39. Simulation with Transport Delay • Example: A 2 Y 1 X 2 C Z 3 B ECE 551 Spring 2003

  40. 2 1 3 5 B=1* Y=1 A=1* B=0* B=0* Z=0 X=0 X=1 Z=1 Simulation with Transport Delay • Linked Event Queue 4 Y=0 X=1 C=1 6 Y=0 Z=1 ECE 551 Spring 2003

  41. Simulation with Transport Delay • Waveforms A B X X Y X X X Z X X X C X X X X X ECE 551 Spring 2003

  42. Simulation with Inertial Delay • What is inertial delay? • Multiple events cannot occur on the output in a time less than the delay. • Example AND with delay = 2 A 1 ns B C Transport Delay C Inertial Delay ECE 551 Spring 2003

  43. Simulation with Inertial Delay • Waveforms A B X X Y X X X Z X X X C X X X X X ECE 551 Spring 2003 1 2 3 4 5 6 7 8

  44. 1 A=1* B=0* X=0 X=1 2 B=1* 3 B=0* 5 Y=1 Z=0 X=1 4 Z=1 X=1 Y=0 Simulation with Inertial Delay • Linked Event Queue Z=1 6 Y=0 C=1 ECE 551 Spring 2003

  45. Simulation with Inertial Delay • Material Moved to previous slide ECE 551 Spring 2003

  46. Verilog Simulation Scheduling Semantics • To be covered later in relation to execution of assignment statements ECE 551 Spring 2003

  47. Stimulus Generation and Response Monitoring • Generic Simulation Structure Response Vectors, Waveforms Test Vectors, Force Files, Waveforms UUT Module Stimulus Response ECE 551 Spring 2003

  48. Testbench Approach - 1 • Use Verilog module to produce testing environment including stimulus generation and/or response monitoring Response Stimulus UUT Module Testbench Module ECE 551 Spring 2003

  49. Stimulus Generation Example 1: `timescale 1ns /1ns module com_test_bench_v; reg[8:0] stim; wire[3:0] S; wire C4; adder_4_b_v a1(stim[8:5], stim[4:1], stim[0], S, C4); //Continued on next slide endmodule ECE 551 Spring 2003

  50. Stimulus Generation Example 1 - 2 //Generate stimulus initial begin stim = 9'b000000000; #10 stim = 9'b111100001; #10 stim = 9'b000011111; #10 stim = 9'b111100010; #10 stim = 9'b000111110; #10 stim = 9'b111100000; #10 stim = 9'b000011110; #10 $stop; end ECE 551 Spring 2003

More Related