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Logic level sequential blocks

Lecture 5.2. Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu www.testgroup.polito.it. Logic level sequential blocks. Goal.

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Logic level sequential blocks

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  1. Lecture 5.2 Paolo PRINETTO Politecnico di Torino (Italy)University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu www.testgroup.polito.it Logic level sequential blocks

  2. Goal • This lecture presents the set of functional sequential blocks that are usually considered to be “elementary” or “basic” at the logic level.

  3. Prerequisites • Module 3 and 4

  4. Homework • No particular homework is foreseen

  5. Further readings • Students interested in making a reference to a text book on the arguments covered in this lecture can refer, for instance, to: • M. Morris Mano, C.R.Kime: “Logic and Computer Design Fundamentals,” 2nd edition updatedPrentice Hall, Upple Saddle River, NJ (USA), 2001, (chapter 4, pp. 182-201)

  6. Further readings or to: • J. P. Hayes:“Introduction to Digital Logic Design,”Addison Wesley, Reading, MA (USA), 1994, (chapter 6, pp. 390-453)

  7. Outline • Latch • Flip-flop • Scannable Flip-flop

  8. Logic level elementary sequential blocks • Devices capable of storing a single bit: • latch • flip-flop system RT logic device behavior structure physical

  9. Latch vs. Flip-flop CLK D

  10. Latch vs. Flip-flop CLK D Q latch

  11. Latch vs. Flip-flop CLK D Q latch flip-flop Q

  12. Pro’s & Con’s • A latch is a Mealy machine • A flip-flop is a Moore machine • Flip-flops improve testability

  13. Latch • A latch is a single-bit storage device implemented as a Mealy machine. • The most widely used is the so called • D latch.

  14. D latch Q 1D IEEE Symbol C1 QN

  15. D latch Q 1D IEEE Symbol C1 QN CharacteristicTable

  16. D latch Q 1D IEEE Symbol C1 QN CharacteristicTable Describes the logical properties of the latch by describing its operation in tabular form

  17. D latch Q 1D IEEE Symbol C1 QN CharacteristicTable C D Q QN 0 - Q-1 QN-1 1 0 0 1 1 1 1 0 Previous value of Q

  18. C D 1S 1R Q QN 0 - 1 1 Q-1 QN-1 1 0 1 0 0 1 1 1 0 1 1 0 Waveforms C D Q

  19. Hazard-free polarity hold latch • Within the in-house developed LSSD design methodology, IBM uses the following implementation: D C Q QN

  20. Set-Reset latch • The Set-Reset latch can be considered the elementary building block for the implementation of all synchronous sequential circuits. • It has: • 2 inputs S and R • 2 output Q and QN, such that QN = Q’. S Q R QN

  21. Set-Reset latch • Of the 4 combinations of S and R: • One forces Q QN = 0 1 (reset) • One forces Q QN = 1 0 (set) • One lets Q QN unchanged • One is forbidden • The Set-Reset latch can be considered the elementary building block for the implementation of all synchronous sequential circuits. • It has: • 2 inputs S and R • 2 output Q and QN, such that QN = Q’. S Q R QN

  22. Set-Reset latch • Of the 4 combinations of S and R: • One forces Q QN = 0 1 (reset) • One forces Q QN = 1 0 (set) • One lets Q QN unchanged • One is forbidden • The Set-Reset latch can be considered the elementary building block for the implementation of all synchronous sequential circuits. • It has: • 2 inputs S and R • 2 output Q and QN, such that QN = Q’. The correspondenceinput combination  performed operationis technology and implementation dependent S Q R QN

  23. Set-Reset latch (nand implementation) S Q R QN

  24. Set-Reset latch (nand implementation) S Q R QN S Q R QN Q-1

  25. Karnaugh Map Set-Reset latch (nand implementation) S R Q-1 • 00 01 11 10 • 0 1 1 0 0 • 1 1 1 1 0 Q

  26. Karnaugh Map CharacteristicTable Set-Reset latch (nand implementation) S R S R Q QN 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q-1 QN-1 Q-1 • 00 01 11 10 • 0 1 1 0 0 • 1 1 1 1 0 Q

  27. Karnaugh Map CharacteristicTable Set-Reset latch (nand implementation) S R S R Q QN 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q-1 QN-1 Q-1 • 00 01 11 10 • 0 1 1 0 0 • 1 1 1 1 0 • This combination is forbidden due to: • It forces both outputs to 1, thus preventing QN = Q’ • a transition • S R = 00 S R = 11 • forces the circuit to enter an unpredictable state, whose value depends from internal delays.

  28. Karnaugh Map CharacteristicTable Set-Reset latch (nand implementation) S R S R Q QN 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q-1 QN-1 Q-1 • 00 01 11 10 • 0 1 1 0 0 • 1 1 1 1 0 Q TransitionTable Q-1 Q S R 0 0 1 - 0 1 0 1 1 0 1 0 1 1 - 1

  29. Set-Reset latch (nor implementation) S Q R QN

  30. Karnaugh Map CharacteristicTable Set-Reset latch (nor implementation) S R Q QN 0 0 Q-1 QN-1 0 1 1 0 1 0 0 1 1 1 0 0 S R Q-1 • 00 01 11 10 • 0 0 1 0 0 • 1 1 1 0 0 Q TransitionTable Q-1 Q S R 0 0 - 0 0 1 0 1 1 0 1 0 1 1 0 -

  31. Gated Set-Reset latch • It’s a variation of the Set-Reset latch, in which data are allowed to enter the latch when a given control signal C is asserted, only. 1S Q Symbol IEEE C1 QN 1R

  32. Possible implementation Si 1S Q C1 Ri QN 1R

  33. Excitation table C1 1S 1R Si Ri Q QN 0 - - 1 1 Q-1 QN-1 1 0 0 1 1 Q-1 QN-1 1 0 1 1 0 0 1 1 1 0 0 1 1 0 1 1 1 0 0

  34. Outline • Latch • Flip-flop • Scannable Flip-flop

  35. Logic level elementary sequential blocks • Devices capable of storing a single bit: • latch • flip-flop system RT logic device behavior structure physical

  36. Flip-Flop • A flip-flop is a single-bit storage device implemented as a Moore machine.

  37. Temporal constraints • Flip-flops works properly iff some temporal constraints are satisfied.

  38. Set-up time The time interval in which data inputs and control inputs must be stable before the clock event

  39. Hold time The time interval in which data inputs and control inputs must be stable after the clock event

  40. FF classification w.r.t. data inputs • According to their behavior w.r.t. data inputs, flip-flops are usually classified as: • D • SR • JK • T.

  41. D behavior CLK Q D Q 0 0 1 1 D QN CharacteristicTable

  42. TransitionTable D Q 0 0 1 1 Q-1 Q D 0 0 0 0 1 1 1 0 0 1 1 1 - 0 0 - 1 1 CharacteristicTable

  43. Caveat • Distinction between data inputs and control inputs is context and application dependent.

  44. Example(D = data input) • At any CLK, it stores the input data D Q CLK

  45. Example(D = control input) • If ( D = 0 ) then force Q=0 else force Q=1 D Q CLK

  46. S R Q QN 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q-1 QN-1 Set-Reset behavior CLK Q S R QN

  47. S R Q QN 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q-1 QN-1 TransitionTable Q-1 Q S R 0 0 1 - 0 1 0 1 1 0 1 0 1 1 - 1 -  0 1 0 -  1 0 1 CharacteristicTable

  48. JK behavior CLK Q J J K Q 0 0 Q-1 0 1 0 1 0 1 1 1 QN-1 K QN

  49. TransitionTable J K Q 0 0 Q-1 0 1 0 1 0 1 1 1 QN-1 Q-1 Q J K 0 0 0 - 0 1 1 - 1 0 - 1 1 1 - 0 - 0 0 1 - 1 1 0 CharacteristicTable

  50. D FF implemented by a JK FF CLK Q D J K QN

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