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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

This session focuses on the intricacies of MOS transistor modeling, especially concerning capacitance variations and threshold dependence influenced by drain-to-source voltage (VDS). We explore the effective resistance, hidden capacitances among gate, source, and drain contacts, and refine our modeling to account for complex interactions. Key topics include capacitance decomposition in strong inversion and subthreshold regions, the impacts of drain-induced barrier lowering (DIBL), and the interplay between capacitance and voltage parameters that affect device performance in digital systems.

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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

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  1. ESE370:Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 29, 2010 MOS Transistors Details

  2. Last Time • Focused on I vs V relationships • Effective resistance • Drive

  3. Today • Capacitance • Gate • Source/Drain Contact • More threshold dependence • VDS

  4. Theme • Refining model • Exploring next level of complexity

  5. Capacitance gate drain src channel • First order: looks like a capacitor • Today: • Like resistance, it is not constant • Capacitance not just to src (drain)

  6. Threshold • Threshold decreases with VDS VT VDS

  7. Capacitance Setup

  8. Capacitance • Argued looked like a capacitor to the channel • …but the channel isn’t really one of our terminals • Don’t connect directly to it.

  9. Capacitance • Four Terminals • How many combinations • 4 things taken 2 at a time

  10. Capacitances • GS, GB, GD, SB, DB, SD

  11. Moving Plates? • What is distance from gate to conductor? • Depletion? • Strong Inversion?

  12. Capacitance Decomposition

  13. Overlap • What is the capacitive implication of gate/src and gate/drain overlap?

  14. Overlap • Length of overlap?

  15. Overlap Capacitance

  16. Overlap Capacitance

  17. Capacitance in Strong Inversion(easy case) • Looks like parallel plate Gate – Channel • What is CGC? • What is CGB?

  18. Capacitance in Strong Inversion • Looks like parallel plate Gate – Channel • What is CGC? • CGB=0

  19. Capacitance in Strong Inversion • But channel isn’t a terminal • Split evenly with source and drain

  20. Capacitance in Strong Inversion • Add in Overlap capacitance

  21. Capacitance Subthreshold • Need to refine model • What showed on Day 9 not quite right • Channel doesn’t start depleted • Starts with substrate doping

  22. Channel Evolution Subthreshold

  23. Capacitance Depletion • What happens to capacitance here? • Capacitor plate distance?

  24. Capacitance Depletion • Capacitance becomes Gate-Body • Capacitance drops

  25. Capacitance vs VGS • G CGC CGCS=CGCD CGCB

  26. Saturation Capacitance?

  27. Saturation Capacitance? • Source end of channel in inversion • Destination end of channel close at threshold • Capacitance shifts to source • Total capacitance reduced

  28. Saturation Capacitance CGC CGCS CGCD VDS/(VGS-VT)

  29. Contact Capacitance

  30. Contact Capacitance • n+ contacts are formed by doping = diffusion • Depletion under contact • Contact-Body capacitance • Depletion around perimeter of contact • Also contact-Body capacitance

  31. Contact/Diffusion Capacitance • Cj – diffusion depletion • Cjsw – sidewall capacitance • LS – length of diffusion LS

  32. Capacitance Roundup • CGS=CGCS+CO • CGD=CGCD+CO • CGB=CGCB • CSB=Cdiff • CDB=Cdiff

  33. One Implication

  34. Step Response? Rsmall Rlarge

  35. Step Response

  36. Impact of CGD • What does CGD do to the switching response here?

  37. Impact of CGD

  38. Threshold

  39. Threshold • Describe VT as a constant • Induce enough electron collection to invert channel

  40. VDS impact • In practice, VDS impacts state of channel

  41. VDS impact • Increasing VDS, already depletes portions of channel

  42. VDS impact • Increasing VDS, already depletes portions of channel • Need less charge, less voltage to invert

  43. Drain-Induced Barrier Lowering (DIBL) VT VDS

  44. DIBL Impact

  45. In a Gate? • What does it impact most? • Which device, which state/operation?

  46. In a Gate • VDS largest for off device • Easier to turn on

  47. In a Gate • VDS largest for off device • Easier to turn on • Leak more

  48. In a Gate • VDS largest for off device • Easier to turn on • Leak more

  49. Admin • HW3 due Friday

  50. Ideas • Capacitance • To every terminal • Voltage dependent • Threshold • Voltage dependent • Generally do manual analysis without CGC VT CGCS VDS CGCB

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