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Digital Integrated Circuits A Design Perspective

This chapter provides an intuitive understanding of semiconductor devices, covering their operation, basic equations, and models for manual analysis and SPICE simulation. It discusses the critical features of p-n junctions in integrated circuits and highlights the significance of energy bands, charge neutrality, and current flow in different regions of a diode. Furthermore, it delves into the challenges posed by sub-micron technology, avalanche breakdown, and the behavior of MOS transistors under various operational conditions, ultimately providing insight into future trends in digital circuit design.

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Digital Integrated Circuits A Design Perspective

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  1. Digital Integrated CircuitsA Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002

  2. Goal of this chapter • Present intuitive understanding of device operation • Introduction of basic device equations • Introduction of models for manual analysis • Introduction of models for SPICE simulation • Analysis of secondary and deep-sub-micron effects • Future trends

  3. B A Al SiO 2 p n Cross-section of pn -junction in an IC process A Al A p n B B One-dimensional representation diode symbol The Diode Mostly occurring as parasitic element in Digital ICs

  4. What is the most important fact(feature) about semiconductor? • 왜 반도체인가? 전도도가 도체와 절연체의 중간이라서? • Ans; 자유전자와 hole 의 공존(에너지 대역 상에서 서로 다른 곳에) • 왜 free electron 과 hole 이 존재하게 되는가? • Fermi 준위가 Band Gap 을 통과하는 물질이 반도체이다. Special names were given to two neighboring E-bands; Others are simply nameless; Conduction band and Valence band as 1st lane and 2nd lane in the 2-lane highway system. • Bound electron has quantized (discrete) E-levels; Perturbation of neighboring atoms in infinitum would produce E-continuum; Periodic structure of crystal lattice yields some screening of the perturbing effects of indirect neighbors yielding E-bands.

  5. @반도체 에서 Energy Gap 이 생기는 이유 • 수소 단원자(Single hydrogen atom) 모델; discrete energy levels • 두 개의 수소 원자 모델; Split Energy levels • N 개의 수소 원자 모델; N 개의 split levels • What happens if N becomes so large?; Energy band and then Energy continuum. • What happens if that is the case with single crystal?; Energy gap appears due to screening effects

  6. Questions to ask now. 1. Why are Q- and Q+ of the same magnitude? 2. Why BV gets smaller with higher doping? 3. How are potential drop divided between n- and p-regions in the depletion region? 4. How does current flow in each region, depletion region, neutral region, and region in between? Depletion Region

  7. MOSFET = MOS capacitor + S/D contact

  8. @PN junction • Charge neutrality; Qp=Qn ->q*Np*Xp=q*Nn*Xn • Va=Vp+Vn • Express Vp, Vn with N, X. • Express BV as a function of Ecrit. • Explain why BV goes low with higher N(Np or Nn).

  9. Diode Current

  10. Forward Bias Lp ; Diffusion Length Forward bias is typically avoided in Digital ICs

  11. Reverse Bias The Dominant Operation Mode

  12. Models for Manual Analysis

  13. Junction Capacitance You can derive this either from C=Es/Xd or from C=dQ/dV Why does LGJ(Linearly-Graded Junction) show less steep Cj Vs. Vd behavior?

  14. Small-signal vs. Large-signal Capacitance • Small-signal; C=Es/Xd, where Xd is a function of V(bias voltage) • Large-signal; verage capacitance is defined by Ceq=(Qj(V1)-Qj(V2))/(V1-V2)

  15. Diffusion Capacitance

  16. Secondary Effects 0.1 ) A ( 0 D I –0.1 –25.0 –15.0 –5.0 0 5.0 V (V) D Avalanche Breakdown For high-doped PN diode, this can be Zener breakdown Due to BTBT(Band-to-Band Tunneling)

  17. Diode Model

  18. SPICE Parameters

  19. |V | GS A Switch! An MOS Transistor What is a Transistor?

  20. The MOS Transistor Polysilicon Aluminum

  21. MOS Transistors -Types and Symbols D D G G S S Depletion NMOS Enhancement NMOS D D G G B S S NMOS with PMOS Enhancement Bulk Contact

  22. Threshold Voltage: Concept

  23. The Threshold Voltage Potential drop for surface inversion Why has NMOS appeared Later than CMOS, i.e., P-well CMOS? Ans; Positive Qss. PMOS, p-well CMOS, NMOS, N-well CMOS, twin-well CMOS

  24. The Body Effect

  25. -4 x 10 6 VGS= 2.5 V 5 Resistive Saturation 4 VGS= 2.0 V Quadratic Relationship (A) 3 VDS = VGS - VT D I 2 VGS= 1.5 V 1 VGS= 1.0 V 0 0 0.5 1 1.5 2 2.5 V (V) DS Current-Voltage RelationsA good ol’ transistor

  26. Transistor in Linear Region

  27. Pinch-off Transistor in Saturation

  28. Current-Voltage RelationsLong-Channel Device

  29. A model for manual analysis parabola

  30. -4 x 10 2.5 VGS= 2.5 V Early Saturation 2 VGS= 2.0 V 1.5 Linear Relationship (A) D I VGS= 1.5 V 1 VGS= 1.0 V 0.5 0 0 0.5 1 1.5 2 2.5 V (V) DS Current-Voltage RelationsThe Deep-Submicron Era Mobility is inversely proportional to the vertical electric field, i.e., gate-source bias

  31. 5 u = 10 sat ) s / m ( n u x = 1.5 x (V/µm) c Velocity Saturation VDsat=Lvsat/mobility Constant velocity Constant mobility (slope = µ)

  32. 10/15 여기서 부터 @만 다시 설명함

  33. @Perspective Vdsat is Vds which launches Ecrit in the channel Explain why Vdsat is low with short-channel MOSFET. I D Long-channel device V = V GS DD Short-channel device V V - V V DSAT GS T DS

  34. -4 x 10 -4 x 10 6 2.5 5 2 4 1.5 (A) 3 (A) D D I I 1 2 0.5 1 0 0 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 V (V) V (V) GS GS ID versus VGS linear quadratic quadratic Long Channel Short Channel

  35. -4 -4 x 10 x 10 2.5 6 VGS= 2.5 V VGS= 2.5 V 5 2 Resistive Saturation VGS= 2.0 V 4 VGS= 2.0 V 1.5 (A) (A) 3 D D VDS = VGS - VT I I VGS= 1.5 V 1 2 VGS= 1.5 V VGS= 1.0 V 0.5 1 VGS= 1.0 V 0 0 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 V (V) V (V) DS DS ID versus VDS Long Channel Short Channel

  36. G S D B @A unified modelfor manual analysis Vmin selects which of the three operating modes Come into play, linear, pinch-off,or velocity saturation. Channel length modulation Channel pinch-off velocity saturation

  37. -4 x 10 2.5 VDS=VDSAT 2 VelocitySaturated 1.5 Linear 1 VDSAT=VGT 0.5 VDS=VGT Saturated 0 0 0.5 1 1.5 2 2.5 @Simple Model versus SPICE 모델과 식의 차이; Vsat onset 이 gradual 하기 때문 (A) D I (Channel pinch-off) V (V) DS

  38. -4 x 10 0 -0.2 -0.4 (A) D I -0.6 -0.8 -1 -2.5 -2 -1.5 -1 -0.5 0 V (V) DS A PMOS Transistor VGS = -1.0V VGS = -1.5V VGS = -2.0V Assume all variables negative! VGS = -2.5V

  39. Transistor Model for Manual Analysis

  40. Subthreshold Conduction • Subthreshold or weak inversion region • Diffusion current due to concentration gradient saturates with Vd of > 0.1 V. • Slope factor; S=n(kT/q)ln(10)

  41. The Transistor as a Switch

  42. The Transistor as a Switch

  43. The Transistor as a Switch

  44. MOS CapacitancesDynamic Behavior

  45. Dynamic Behavior of MOS Transistor

  46. Polysilicongate Source Drain W x x + + n n d d Gate-bulk L d overlap Top view Gate oxide t ox + + n n L Cross section The Gate Capacitance

  47. Gate Capacitance Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off

  48. Gate Capacitance Accumulation region Inversion with source/drain electron Cgc=Cgcb+Cgcs+Cgcd Cgb=0 Capacitance as a function of the degree of saturation Capacitance as a function of VGS (with VDS = 0)

  49. @Extracting the SPICE parameter by Measuring the Gate Capacitance Apply const I, and measure V(t) to obtain C.

  50. Diffusion (Junction) Capacitance Channel-stop implant N 1 A Side wall Source W N D Bottom x Side wall j Channel L Substrate N S A

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