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Clock Upset and Finite State Machines

This study examines the vulnerability of finite state machines (FSMs) to Single Event Transients (SETs) induced by heavy ion strikes. SETs can cause clock upsets that may lead to multiple bit errors and affect error correction techniques like parity and Hamming codes. Key findings include critical transient width versus feature size, the significance of clock tree buffers, and the potential for error mitigation through temporal sampling latches. Recommendations for hardening FSMs against SETs are provided along with insights into the trade-offs required in high-radiation environments.

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Clock Upset and Finite State Machines

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  1. Clock UpsetandFinite State Machines

  2. Single Event Transient (SET) Fraction of a nanosecond to several nanoseconds. From Aerospace

  3. Critical Transient Width vs FeatureSize for Unattenuated Propagation From Mavis

  4. Heavy Ion Hit Transient Pulse Passed One Buffer Data In Mode 1 Transient Upset • Transient pulse higher than half VDC will propagate • Qcrit ~ 0.02pC, or LETth ~ 2MeV-cm2/mg for the worst case

  5. Double Clocking As a Result of Heavy Ion Induced Pulse Heavy ion induced negative pulse Cartoon of clock/logic upset. The device is most sensitive during the transition.

  6. Simulated Upsets for Various LETs Can get narrow and runt pulses.

  7. Row Buffer Input Pad (14 Rows) Clock Buffer Clock Tree BuffersSensitive to SETs Heavy Ion

  8. Clock Upset Instrumentation Differential Error Counts Cumulative Error Counts

  9. Clock Upset Cross Section

  10. Frequency Dependence of Clock Upset

  11. Clock Trees Can Be Hardened

  12. Temporal Sampling Latch with Sample and Release Stages From Mavis

  13. Temporal Latch Control Clocks Derived from Master Clock From Mavis

  14. Effects on Finite State Machines • Can cause the equivalent of multiple bit error • Can defeat parity, Hamming Codes, TMR, etc.

  15. References • "Clock buffer circuit soft errors in antifuse-based field programmable gate arrays, Jih-Jong Wang; Katz, R.B.; Dhaoui, F.; McCollum, J.L.; Wong, W.; Cronquist, B.E.; Lambertson, R.T.; Hamdy, E.; Kleyner, I.; Parker, W., IEEE Transactions on Nuclear Science, Dec., 2000. • "Temporally Redundant Latch for Preventing Single Event Disruptions in Sequential Integrated Circuits," David G. Mavis and Paul H. Eaton, Mission Research Corporation, Technical Report P8111.29, September 1998 (revised October 1998).

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