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Raimund Kirner this is joint work with Martin Schöberl and Peter Puschner

Single-Path Programming on a Chip-Multiprocessor System RePP 2009 : Workshop on Reconciling Performance with Predictability. Raimund Kirner this is joint work with Martin Schöberl and Peter Puschner. How do we know the timing is right?. ?. response time. Environment. RTCS. 2.

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Raimund Kirner this is joint work with Martin Schöberl and Peter Puschner

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  1. Single-Path Programming on aChip-Multiprocessor SystemRePP 2009 : Workshop on Reconciling Performance with Predictability Raimund Kirner this is joint work with Martin Schöberl and Peter Puschner

  2. How do we know the timing is right? ? response time Environment RTCS 2

  3. How do we know the timing is right? ? WCET analysis (local system behavior) WCET analysis (local system behavior) WCET analysis (local system behavior) WCET analysis (local system behavior) WCET analysis (local system behavior) schedulability analysis (global system behavior) response time Environment RTCS 3

  4. The State of the Art on WCET Analysis Despite 20 years of research, there are still serious open problems in WCET analysis Most challenging problem: high complexity of today’s processors Manual interaction with the user is required for path analysis. Industrial SW development tools lack comprehensive support for WCET analysis 4

  5. Current Trend: Multi-Core Computing Adds to the complexity of system design and verification! Without careful hardware design towards predictability, WCET analysis is much more complex! Timing interaction between different cores should be avoided whenever possible Design pattern: “Temporal Firewalls” 5

  6. Our Approach Multi-core computing Reference platform:JOP (Java Optimized Processor) Prioritized goals: Temporal predictability / stability first Performance second 6

  7. Hardware: JOP Chip-Multiprocessor Legend:M: local method cache S: local stack cache SPM: local scratchpad memory 7

  8. The Task Model Simple tasks (no blocking of a task) [Kopetz97] Periodic task activation (time-triggered) Inter-process communication with shared memory A task run consists of three phases: read (only read shared memory) exec (no access to shared memory) write (only write to shared memory) 8

  9. The Programming Model Single-path (SP) computing (use of conditional data-flow instead of conditional control-flow) SP computing doesn’t have to be explicitly programmed automatic transformation of programs into SP programs possible (by compiler) WCET-oriented programming- includes SP computing as a pattern 9

  10. Single-Path Transformation Transform input-data dependent branches into sequential predicated code, rest remains unchanged Technique based on: if-conversion if cond P := cond (P) res := expr1 (not P) res := expr2 res := expr1 res := expr2  Predicated execution 10

  11. Hardware Support for Single-Path Programming String a = ”true” ; String b = ” false ” ; String result ; int val ; boolean cond = true; val = Native.condMove(1, 2, cond); System.out.println(val ); result = (String) Native.condMoveRef(a, b, cond); System.out.println( result ); 11

  12. Hardware Support for Time-Predictable Task Activation SysDevice sys = IOFactory.getFactory().getSysDevice(); int time = sys. cntInt ; time = time – (time % TDMA) + 1000; sys.deadLine = time; “sys.deadLine = time” blocks until the deadline is reached Maximum jitter without synchronization to the memory arbiter: length of TDMA round - 1 12

  13. Example: Safety-Critical Control Application 13

  14. Example: Complex Communications 14

  15. Example: Multi-Core Scheduling • Task Phases: • Read • Exec • Write C D C A+B A+B D E A+B Task List: A … STSampler τ1 B … STSampler τ2 C … STController τ3 D … STGuard τ4 E … STMonitor τ5 E E D A+B A+B A+B C 15

  16. Example: Measured SP Exec. Times 16

  17. Conclusion and Outlook Ultra time-predictable hardware/software approach Inter-core communication with global memory No system-on-chip networking Synchronized task activation relative to TDMA –based memory arbiter Local caches on each core to improve TDMA-based memory access performance Tool support desired for creating efficient time-predictable schedules 17

  18. Special Issue on WCET AnalysisCall for Contributions • Journal of Systems Architecture (Elsevier) • Editors: Andreas Ermedahl, Peter Puschner • Important Dates: January 10, 2010 Submission Deadline July 1, 2010 Journal in print • Web: www.elsevier.com/locate/sysarc

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