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CMOS Manufacturing Process

CMOS Manufacturing Process. DD. M. 2. V. in. M. 1. CMOS Process. A Modern CMOS Process. Dual-Well Trench-Isolated CMOS Process. Circuit Under Design. This two-inverter circuit will be. manufactured in a twin-well process. Circuit Layout. The Manufacturing Process.

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CMOS Manufacturing Process

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  1. CMOSManufacturingProcess

  2. DD M 2 V in M 1 CMOS Process

  3. A Modern CMOS Process Dual-Well Trench-Isolated CMOS Process

  4. Circuit Under Design This two-inverter circuit will be manufactured in a twin-well process.

  5. Circuit Layout

  6. The Manufacturing Process These slides only present only a couple of snapshots of the manufacturing process for the circuits presented in the textbook. For a complete overview of all steps, please refer to: http://www.fullman.com/semiconductors/semiconductors.html

  7. Photo-Lithographic Process optical mask oxidation photoresist photoresist coating removal (ashing) stepper exposure Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process spin, rinse, dry step

  8. Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers CMOS Process at a Glance

  9. Starting wafer: n-type with doping level = 10 13 3 /cm Start Material A A’ * Cross-sections will be shown along vertical line A-A’

  10. N-well Construction (1) Oxidize wafer (2) Deposit silicon nitride (3) Deposit photoresist

  11. N-well Construction (4) Expose resist using n-well mask

  12. N-well Construction (5) Develop resist (6) Etch nitride and (7) Grow thick oxide

  13. N-well Construction (8) Implant n-dopants (phosphorus) m (up to 1.5 m deep)

  14. P-well Construction Repeat previous steps

  15. Grow Gate Oxide 0.055 mm thin

  16. Grow Thick Field Oxide 0.9 mm thick Uses Active Area mask Is followed by threshold-adjusting implants

  17. Polysilicon layer

  18. Source-Drain Implants

  19. Source-Drain Implants

  20. Contact-Hole Definition (1) Deposit inter-level dielectric (SiO2) — 0.75 mm (2) Define contact opening using contact mask

  21. Aluminum-1 Layer Aluminum evaporated (0.8 mm thick) followed by other metal layers and glass

  22. Advanced Metalization

  23. Advanced Metallization

  24. Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers CMOS Process at a Glance

  25. Design Rules

  26. MOS Transistor 3-D perspective

  27. Design Rules • Interface between designer and process engineer • Guidelines for constructing process masks • Unit dimension: Minimum line width • scalable design rules: lambda parameter • absolute dimensions (micron rules)

  28. Layer Color Representation Well (p,n) Yellow Active Area (n+,p+) Green Select (p+,n+) Green Polysilicon Red Metal1 Blue Metal2 Magenta Contact To Poly Black Contact To Diffusion Black Via Black CMOS Process Layers

  29. Layers in 0.25 mm CMOS process

  30. Intra-Layer Design Rules 4 Metal2 3

  31. Transistor Layout

  32. Via’s and Contacts

  33. Select Layer

  34. CMOS Inverter Layout

  35. Layout Editor

  36. Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um.

  37. V DD 3 Out In 1 GND Stick diagram of inverter Sticks Diagram • Dimensionless layout entities • Only topology is important • Final layout generated by “compaction” program

  38. MOS Devices

  39. |V | GS A Switch! An MOS Transistor What is a Transistor?

  40. The MOS Transistor Polysilicon Aluminum

  41. MOS Transistors -Types and Symbols D D G G S S Depletion NMOS Enhancement NMOS D D G G B S S NMOS with PMOS Enhancement Bulk Contact

  42. Threshold Voltage: Concept

  43. The Threshold Voltage Potential drop across the depletion region

  44. Threshold Voltage Example Oxide Capacitance: Body Effect: For VT0 = 0.75,  = 0.54, 2F = - 0.6 V, and VSB = 5 V VT(5 V) = 0.75 V + 0.86 V = 1.6 V

  45. The Body Effect

  46. -4 x 10 6 VGS= 2.5 V 5 Resistive Saturation 4 VGS= 2.0 V Quadratic Relationship (A) 3 VDS = VGS - VT D I 2 VGS= 1.5 V 1 VGS= 1.0 V 0 0 0.5 1 1.5 2 2.5 V (V) DS Current-Voltage RelationsA good ol’ transistor

  47. Transistor in Linear

  48. Pinch-off Transistor in Saturation

  49. Current-Voltage RelationsLong-Channel Device

  50. A model for manual analysis

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