1 / 16

Advanced Logic Design: Synthesis of Combinational Logic (Lecture 12)

This lecture covers the synthesis of combinational logic, focusing on logic synthesis techniques and Boolean descriptions. Key topics include RTL synthesis, behavioral synthesis, and optimization engines. Students will learn about the translation process from Verilog to Boolean equations and explore logic optimization strategies such as substitution, factoring, decomposition, extraction, and elimination. Additionally, practical examples illustrate the delay and area considerations in combinational logic designs, incorporating Verilog module exercises and finite state machine applications.

les
Télécharger la présentation

Advanced Logic Design: Synthesis of Combinational Logic (Lecture 12)

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ELEN 468Advanced Logic Design Lecture 12 Synthesis of Combinational Logic I ELEN 468 Lecture 12

  2. Synthesis • Logic synthesis • Boolean descriptions => circuits • RTL synthesis • RTL descriptions => Boolean descriptions • Behavioral synthesis • Behavioral descriptions => RTL descriptions ELEN 468 Lecture 12

  3. Objective of Synthesis Delay Area ELEN 468 Lecture 12

  4. Logic Synthesis Behavioral Descriptions Technology Libraries Translation Engine Optimization Engine Mapping Engine Technology Implementation Two-level Logic Functions Optimized Multi-level Logic Functions ELEN 468 Lecture 12

  5. Translation Engine • Read in Verilog-based descriptions • Translate into Boolean equations • SOP – sum of product • POS – product of sum • A Verilog description consisting only of a netlist of combinational primitives without feedback can always be synthesized ELEN 468 Lecture 12

  6. Logic Optimization • Remove redundant logic, exploit logic sharing • Substitution • Factoring • Decomposition • Extraction • Elimination/flattening ELEN 468 Lecture 12

  7. Substitution Express a Boolean function in terms of its inputs and another function G = a + b F = a + b + c G = a + b F = G + c ELEN 468 Lecture 12

  8. Factoring Find the common factors among a set of functions F = ac + ad + bc + bd + e F = ( a + b ) ( c + d ) + e Two-level => multi-level Area reduced Delay increased ELEN 468 Lecture 12

  9. Decomposition Express one Boolean function in terms of new nodes F = abc + abd + a’c’d’ + b’c’d’ 9 gates, 40 transistors F = XY + X’Y’ X = ab Y = c + d 7 gates, 24 transistors Figure 8.6, 8.7, page 287 ELEN 468 Lecture 12

  10. Extraction Express a set of Boolean functions in terms of new nodes F = ( a + b ) cd + e G = ( a + b ) e’ H = cde X = a + b Y = cd F = XY + e G = Xe’ H = Ye ELEN 468 Lecture 12

  11. Elimination / Flattening Remove a node in a function Increase area Reduce delay F = Ga + G’b G = c + d F = ac + ad + bc’d’ ELEN 468 Lecture 12

  12. Combinational Logic Delay Combinational logic delay <= clock period Register Primary Input Register Primary Output Combinational Logic clock ELEN 468 Lecture 12

  13. Synthesis Support to Verilog • Commonly supported • Figure 8.17, page 297 • Unsupported • Figure 8.18, page 298 ELEN 468 Lecture 12

  14. Exercise 3 ELEN 468 Lecture 12

  15. Find Delay module M ( y, a, b, c ); output y; input a, b, c; and #(2, 4) (w1, a, b); not #3 (w2, c); nor #(5, 2 ) (y, w1, w2); endmodule a -> y (9, 4) b -> y (9, 4) c -> y (8, 5) ELEN 468 Lecture 12

  16. FSM of Traffic Light Control module traffic ( light, clock, pedx ); input clock, pedx; output [1:0] light; reg [1:0] light; reg [7:0] timer; parameter green = 2`b01; parameter yellow = 2`b10; parameter red = 2`b11; always @ ( timer ) begin if ( timer < 100 ) light <= green; else if ( timer < 110 ) light <= yellow; else light <= red; end always @ ( posedge clock ) begin if ( timer < 130 ) timer <= timer+ 1; else timer <= 0; end always @ ( posedge pedx ) if ( light == green ) timer <= 100; endmodule ELEN 468 Lecture 12

More Related