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An ATCA and FPGA-Based Data Processing Unit for PANDA Experiment

An ATCA and FPGA-Based Data Processing Unit for PANDA Experiment. H.XU, Z.-A. LIU ,Q.WANG, D.JIN, Inst. High Energy Physics, Beijing, W. Kühn, J. Lang, S. Lange, M. Liu, II Physikalisches Institut, Univ. Giessen. RT2010, Lisbon May. 24 2010. Overview. Requirements for PANDA TDAQ

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An ATCA and FPGA-Based Data Processing Unit for PANDA Experiment

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  1. An ATCA and FPGA-Based Data Processing Unit for PANDA Experiment H.XU, Z.-A. LIU,Q.WANG, D.JIN, Inst. High Energy Physics, Beijing, W. Kühn, J. Lang, S. Lange, M. Liu, II Physikalisches Institut, Univ. Giessen. RT2010, Lisbon May. 24 2010

  2. Overview • Requirements for PANDA TDAQ • Interaction rates up to 30MHz • typical event sizes 4 - 20 kB. • data rates after front end preprocessing: 40GB/s - 200 GB/s • high flexibility and selectivity • Solution: • continuously sampling data acquisition • No „hardware triggers“ • Precision clock distribution system • Digital signal processing at FrontEnd level • Event selection in programmable processing units • Connection via high speed networks • PANDA Experiment at FAIR • High Rates • σ ~ 55 mb • 3x107 interactions/s • Micro Vertexing • Charged particle ID • – (e±,μ±,π±,p,…) • Tracking /TPC • EM. Calorimetry • (γ,π0,η) • Forward capabilities • (leading particles) • Sophisticated event selection Zhen'An LIU, IHEP/Beijing

  3. Data Rates and Event Sizes Zhen'An LIU, IHEP/Beijing

  4. Structure of PANDA TDAQ • TDAQ block diagram • General Purpose Data Processing Unit(GPDP) • Highly scalable to adapt to different performance and bandwidth requirements • Computing resources via FPGA: XILINX Virtex4 FX60 • Lots of buffer memory • Flexible I/O connectivity • GBit Ethernet • Optical links via MGT (RocketIO) • High performance backplane interconnection • XTCA compliant • ATCA full mesh backplane Zhen'An LIU, IHEP/Beijing

  5. Basic Functions of GPDP: FPGA based Zhen'An LIU, IHEP/Beijing

  6. Architecture and features of GPDP • High Performance Compute Power/resources: • 5 Virtex-4 FX60 FPGA • 10Gb DDR2 RAM (2G/FPGA) • ~32Gbps Bandwidth • 8x panel Optical Link • 13x RocketIO to backplane • 5x Gigabit Ethernet • 1x GBit Ethernet to backplane • 2 Embedded PowerPC in each FPGA for slow control • Real time Linux • XTCA compliant Zhen'An LIU, IHEP/Beijing

  7. First Prototype FPGA #1-4 FPGA #O Optical Backplane Ethernet DDR2 sockets Zhen'An LIU, IHEP/Beijing

  8. 2nd version prototype • SFP pluggable • Mono RJ45 socket • Higher bandwidth /SFP+ • Front Pannel • Better LEDs Zhen'An LIU, IHEP/Beijing

  9. New version under development • AMC for processor FPGA • More memory 4Gb/FPGA(total of 20Gb) • Clocks and controls • Clocks • Trigger • Control • Higher bandwidth • Full SFP+ Zhen'An LIU, IHEP/Beijing

  10. IPMC • Daugter board • I2C bus • Monitoring • Temperature • Voltages • Power consumption Zhen'An LIU, IHEP/Beijing

  11. Embedded System Architecture (FX60) Zhen'An LIU, IHEP/Beijing

  12. Development setup Zhen'An LIU, IHEP/Beijing

  13. Summary and Outlook • Status: • Continuous sampling DAQ, no hardware triggers, high level event selection • Universal building block: General Purpose Data Processor • 2 prototype versions built and production ready for PANDA • first algorithms have been implemented • demonstrator system (HADES@FAIR) • Single ATCA shelf replaces ~ 10 VME crates • Up to 13 CN + 1 CPU module • Implementation of DAQ and trigger algorithm firmware for: • HADES @ FAIR • Use as a prototype DAQ for PANDA detector tests Zhen'An LIU, IHEP/Beijing

  14. Summary and Outlook(2) • Further development • XTCA compliant • 20 GB memory • Clock and controls • Belle II PXD application • 2010/11 Algorithm development for PANDA • 2012-14 Construction and commissioning of PANDA DAQ Zhen'An LIU, IHEP/Beijing

  15. Much Thanks for Your Attention! Zhen'An LIU, IHEP/Beijing

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