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T2.3 Task

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T2.3 Task

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  1. T2.3 Task Task T2.3: Electrical characterization of PV, software (TCAD) / hardware comparison & calibration • Basic effects of PV will be characterized based on hardware in different technologies, ranging from mainstream CMOS 45/32nm to new device architectures suitable for 22nm CMOS. • Other technologies like NVM or SiC, GaAn/AlGaN power and RF devices will complement the activities. In addition for “non pure digital logic technologies” the devices studied will span over many technology generations, so the PV-methodologies will cover a wide spectrum of devices. In general major sources for PV will be identified and characterized wrt/ further scaling. • Variability effects and their sensitivities will be investigated from planar bulk device concepts to new architectures on SOI in 2D or 3D. • Device simulation results will be compared to measurements and will be calibrated on hardware data to verify PV methodology and physical understanding of major sources of PV in above technologies. • Partners: NXP, AMS, IMEP, UNET, LETI, NMX, STF2, ST-I Project Review Meeting Crolles, June 22, 2009

  2. Electrical Characterization: T2.3 Deliverables Task Leader: hans.tuinhout@nxp.com Project Review Meeting Crolles, June 22, 2009

  3. WP2 T2.3 Review • Contributor: ST-F (Bajolet) • Activity done so far • Progress: "Characterization of the influence of variability sources in planar bulk CMOS devices down to 45nm" , the choice of the appropriate silicon and structures has been done and measurements are in progress. • Status: on track • Plan for D2.3.1 D2.3.2 deliverables • Results should be available in time for D2.3.1 (M12) deliverable. • Issues • Near term (for D2.3.1 D2.3.2 deliverable): so far no issue • Mean term: so far no issue • Interaction need with other WP, if any: not reported Project Review Meeting Crolles, June 22, 2009

  4. WP2 T2.3 Review • Contributor: IMEP (Ghibaudo) • Activity done so far • IMEP is involved in the electrical characterization of variability in advanced CMOS devices (bulk and thin film SOI) • develop new methodologies for the measurements of MOSFET parameter variability (metal gate work function, thin film thickness variation, noise, etc.) based on experimental procedures and data analysis on various CMOS technologies with bulk or thin film architectures. • This work will be carried out in collaboration with ST . • Paper presented at ULIS (Mezzomo et al) • Plan for D2.3.1 D2.3.2 deliverables (not reported; ontrack?) • Issues • Near term (for D2.3.1 D2.3.2 deliverable): no issue reported • Mean term: no issue reported • Interaction need with other WP, if any: not reported Project Review Meeting Crolles, June 22, 2009

  5. WP2 T2.3 Review • Company/Contributor: NXP (Tuinhout) • Activities done so far • new 45 nm transistor matching test chip available; first 45 silicon measured • excellent material for assessment of random PV analysis and proximity effects • tuning of device simulator (SWB) ongoing although formally outside MODERN • excellent FinFET material available although NXP officially stopped • Plan D2.3.1: • analyze 90-65-45 trends & classify proximity variability sources • summarize FinFET results (?) • Plan D2.3.2: start 1/f dispersion measurements in september (on track) • Near term (for D2.3.1 D2.3.2 ) & Medium term Issues • progress may depend on NXP company re-design and work/program priorities • Interaction: compare / align device simulator tuning procedures (although formally outside MODERN for NXP) Project Review Meeting Crolles, June 22, 2009

  6. WP2 T2.3 Review • Company/Contributor:NMX (Vendrame) • Activity done so far • Progress: in this task NMX is involved in test structures design and measurement with focus on specific analogue characterization of the logic devices of NVM technologies (e.g. long distance matching measurements, etc). • Status: characterization started on available test structures and preliminary measurement analysis running in cooperation with UNET (Ferrara unit). • Plan for deliverables : D2.3.1 preliminary results will be givenD2.3.2 not involved • Issues • Near term under discussion cooperation with STF (link WP2.3 – WP 5.1) • open to other cooperation • Interaction need with other WP, if any: NMX activities are linked at different extent and abstraction levels with the following WPs and Tasks in which we are involved: 2.2, (2.3 this one), 2.5, 3.2, 4.3, 5.1, also under discussion interaction with other partners (UNI-Glasgow, etc) Project Review Meeting Crolles, June 22, 2009

  7. WP2 T2.3 Review • Company/Contributor: IUNET-MI&FE (Pavan) • Activity done so far • Progress: started characterization of bit distribution in memory cells • Status : started characterization of bit distribution in memory cells. • Plan for deliverables : • D2.3.2: trying to identify the effects of the different contributions to PV • Issues • none • Interaction need with other WP, if any: no points reported Project Review Meeting Crolles, June 22, 2009

  8. WP2 T2.3 Review Overview / Conclusions • No reactions received from • UNET on 45 nm bulk status • LETI on FD-SOI • ST-I on SiC and AlGaN/GaN devices • Plan for deliverables D2.3.1 & D2.3.2 : no roadblocks reported / foreseen • should we plan a contact meeting to share & compare results (D2.3.1) • Issues • NMX: Near term under discussion cooperation with STF (link WP2.3 – WP 5.1) • NXP: FinFET research oficially stopped • Interaction need with other WP, if any: - UGLA (T2.2) stresses that measured device geometries should be aligned with simulated ones - NXP sees benefit of suggests sharing of simulator tuning approach Project Review Meeting Crolles, June 22, 2009