1 / 19

Power Electronics

Power Electronics. Power amplifiers. Figure 12.1-2. Thermodynamic context of power amplifier . Figure 12.1–2. Thermal resistances. . Figure 12.1–2 Maximum power hyperbolae for power transistors .

mahon
Télécharger la présentation

Power Electronics

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Power Electronics Power amplifiers

  2. Figure 12.1-2. Thermodynamic context of power amplifier

  3. Figure 12.1–2. Thermal resistances.

  4. Figure 12.1–2 Maximum power hyperbolae for power transistors

  5. Figure 12.3–1 The pin junction: (a) Cross–section (b) Potentials and E–fields in reverse–bias (c) Injected carrier levels in forward bias

  6. Figure 12.4–1 Class-A circuit using BJT drivers.

  7. Figure 12.4–2. (a) Class-A circuit consisting of BJT driver and simple current mirror. (b) Waveforms for the class-A amplifier.

  8. Figure 12.5–1. Class-B topology with complementary push-pull BJTs

  9. Figure 12.5-2. For purposes of plot analysis we have let VS = 10V. By inspection it appears that VL (worst) is approximately at 6.4V. And this is confirmed by equation 12.5-5 (below).

  10. Figure 12.7–1. Crossover distortion effects with class-B

  11. Figure 12.7–3. Principles of the class-AB amplifier.

  12. Figure 12.7–2. Class-AB diode bias of transistor pair

  13. Figure 12.7–5: Class-AB Darlington configurations, VBE biasing.

  14. Figure 12.7–3. The Darlington pair IE2 = (2 +1) x IE1

  15. IE2 = (2 +1) x (IE1 – IR1) IE2 = (2 +1) x (IC1 – IR2) IE2 = (2 +1) x IC1

  16. Figure 12.9–1. Circuits configurations using stacked power opamps and input buffer

  17. Figure 12.9–2. The power bridge: (a) the opamp pair (b) output transistor operation.

  18. Figure 12.10–2a. PWM (pulse-width modulation) circuit for front end of class-D amplifier. Figure 12.10–2b. Use of sawtooth to accomplish PWM

More Related