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A spreadsheet-based simulation of CPU instruction execution

A spreadsheet-based simulation of CPU instruction execution. R. E. Smith Computer & Computational Science University of St. Thomas St. Paul, MN. The Spreadsheet CPU. Motivation – teaching about the CPU Overview – using a spreadsheet Literacy Version Architecture Version Fetch Cycle

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A spreadsheet-based simulation of CPU instruction execution

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  1. A spreadsheet-based simulation of CPU instruction execution R. E. Smith Computer & Computational Science University of St. Thomas St. Paul, MN R. Smith - University of St Thomas - Minnesota

  2. The Spreadsheet CPU • Motivation – teaching about the CPU • Overview – using a spreadsheet • Literacy Version • Architecture Version • Fetch Cycle • Execute Cycle R. Smith - University of St Thomas - Minnesota

  3. Teaching about the CPU • Literacy – how a CPU works • Fetch-Execute Cycle – what the Gigahertz count • Registers and RAM • Machine language programming • Architecture – how instructions work • Mechanism for instruction decoding and execution • Modifying the instruction set – adding and changing R. Smith - University of St Thomas - Minnesota

  4. Using a spreadsheet • Why: Students are familiar with them • Cells provide a visual representation of RAM • Functional semantics via the “Value Rule” • Contrast with machine language semantics • How: Implementing the behavior • Use a column of cells as RAM • Separate columns for “fetch” and “execute” cycles • Use a ‘macro’ to cycle the state machine • Separate cells for “last state” and “next state” • Each register has its own row R. Smith - University of St Thomas - Minnesota

  5. Literacy version R. Smith - University of St Thomas - Minnesota

  6. Architecture Version • Goals • Better instruction set: conditionals, indexing • Easy for students to follow instruction execution • Easy for students to modify instructions • First attempt • Instructions assigned to separate columns • Registers/cycles split into separate rows • Hard to explain and modify • Current version • Separate “sheets”/tabs for each instruction cycle • Easier to add a “defer” cycle for indirection, if desired R. Smith - University of St Thomas - Minnesota

  7. Architecture Version: Fetch Cycle R. Smith - University of St Thomas - Minnesota

  8. Execute Cycle R. Smith - University of St Thomas - Minnesota

  9. Demonstration R. Smith - University of St Thomas - Minnesota

  10. Instruction Set R. Smith - University of St Thomas - Minnesota

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