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Stelio Montebugnoli IRA -INAF- Bologna –Italy-

DS-6. Stelio Montebugnoli IRA -INAF- Bologna –Italy-. SKADS 4th -Lisbon- Oct 2-3, 2008. DS-6 is composed by: - DS-6 T1 Design of subsystem DS-6 T2 Development and demonstration DS-6 T3 Assessment of performance DS-6 T4 Phased array on concentrators.

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Stelio Montebugnoli IRA -INAF- Bologna –Italy-

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  1. DS-6 Stelio Montebugnoli IRA -INAF- Bologna –Italy- SKADS 4th -Lisbon- Oct 2-3, 2008

  2. DS-6 is composed by: • - DS-6 T1 Design of subsystem • DS-6 T2 Development and demonstration • DS-6 T3 Assessment of performance • DS-6 T4 Phased array on concentrators

  3. DS-6 E/W  24 mt 4 receivers  110 mt F=408 MHz @ 16 MHz N/S BEST-1: 170 sqm 4 Rx BEST-2 : 1400 sqm 32 Rx BEST-3: 3200 sqm 60 Rx (14 cylinders +1 E/w 24 mt line) equivalent to a 64 mt diameter dish

  4. DS-6: Basic architecture & related blocks A/D & Data Proc. OP. Tx OP. Rx F.E. IF optical fiber LO distributor LO Sync • F.E. Developed • Single end front end • Differential front end • Balanced front end • Main requirements: • - Low cost • Low noise • Reliable • High dynamic range Synth. (More details are reported in the J. Monari talk)

  5. RELIABILITY PREDICTION Florence College of Engineering • Reliabilty prediction exercise for the front end • The analysis hasbeen implemented by means of MIL-HDBK-217H reliability database • Hypothesis: • Reliability Block Diagram: series configuration • 100% Duty cycle • Operating Temperature: 40°C • Operating environment: MilStd Ground Mobile (Front-end) and • MilStd Ground Fixed Uncontrolled (Downconversion) Reliability Data (MTBF) Front-end: 127365 hours 14.5 Years By the evaluation of MTBF (Mean Time Between Failures) variations while still in the project design phase, it is possible to increase the system reliability.

  6. DS-6: Basic architecture & related blocks A/D & Data Proc. optical fiber OP. Tx OP. Rx F.E. IF LO distributor LO Sync Synth. Optical Tx Optical Rx

  7. DS-6: Basic architecture & related blocks A/D & Data Proc. optical fiber OP. Tx OP. Rx F.E. IF LO distributor LO Sync Synth. … VCSEL represents the only way to reduce costs of the optical link. IRA plans for a prototype at the end of SKADS but it is not clear the role that ANDREW and MITEQ will play in this task. • Collaboration with ANDREW WIRELESS SYSTEMS and MITEQ on analogue optical links will last till the end of SKADS • IRA is collaborating with : • AWS  on the test of a 4.5 GHZ Tx, equipped with a cooled Laser. • MITEQ  to optimize a standard commercial products to satisfy the requirements. A plan to design an ad hoc low cost optical link is considered as well. (More details are reported in the F. Perini talk)

  8. DS-6: Basic architecture & related blocks optical fiber A/D & Data Proc. OP. Tx OP. Rx F.E. IF LO distributor LO Sync Synth. Div x 8 Xmas tree OL distribution

  9. DS-6: Basic architecture & related blocks optical fiber A/D & Data Proc. OP. Tx OP. Rx F.E. IF LO distributor LO Sync Synth. A/D & Data Proc. OP. Tx OP. Rx A/Filt. F.E. optical fiber RF Direct Digitization …potentially possible with the “Casper” system… BEST works at 408 MHz and the A/D can sample at more the 1 GS/s. Sync Synth.

  10. DS-6: Basic architecture & related blocks optical fiber A/D & Data Proc. OP. Tx OP. Rx F.E. IF LO distributor LO Sync Synth. IF Input of Optical fibre

  11. DS-6: Basic architecture & related blocks optical fiber A/D & Data Proc. OP. Tx OP. Rx F.E. IF LO distributor LO Sync . Sync x 32 for A/Ds

  12. Architecture and technology for immediate application on the BEST - x demonstrator construction (T0+10mo). From Sensor Low Noise balanced Amplifier IF Amplifier Optical Fiber To A/D & Signal Proc.

  13. DS-6: Basic architecture & related blocks optical fiber A/D & Data Proc. OP. Tx OP. Rx F.E. IF LO distributor LO Sync . For the A/Ds and post processing blocks, the Berkeley-CASPER Boards have been used….

  14. DS-6: Basic architecture & related blocks A/D and data Processing A/D+ IBOB CASPER system : A/D+ IBOBs + Bee2 Our collaboration is starting with South Africa and Berkeley Wide band A/D converter: dual 8 bits @ 1 GS/Sec converter (4 A/D for each IBOB packetizer board FPGA Wide band A/D

  15. DS-6: Basic architecture & related blocks A/D and data Processing Xilinx Virtex 2 Pro 70 (100 as well) • One Bee2 board can deliver 500 GOps/sec with a 400 W power supply. • 6.7 MOps /€ • 1.25 GOps/W

  16. DS-6: Basic architecture & related blocks A/D and data Processing A 32 receivers FX correlator (2048 ch) has been programmed in 1 week time in the frame of a colalboration starting from South Africa (Alan Langman, Jason Manley), IRA and Berkeley (D. Werthimer, Aaron Parsons).

  17. DS-6: Basic architecture & related blocks Basic FX Correlator block diagram Z-n FFT Z-n Z-n FFT FFT ∑ ∑ ∑

  18. DS-6: Basic architecture & related blocks Basic Modular FX Correlator block diagram

  19. DS-6: Basic architecture & related blocks FX correlator with Bee-2 • Complex multiply allows for fine delay control and per • channel digital gain control • - White coloured blocks not yet implemented

  20. DS-6: Basic architecture & related blocks CAS. A, 1 h of data 1-2 interferometer Rx1, Rx 2 baseline (outermost receivers). The fringes are clearly visible. However, the RFI are quite big.

  21. DS-6: Basic architecture & related blocks CAS. A, 1 h of data 1-2 interferometer …… with the RFI flagged. The fringes are now clean.

  22. DS-6: Basic architecture & related blocks CAS. A, 1 h of data CAS. A, 1 h of data CAS.A with strong RFIs (Tv station in the lower part of the band)

  23. DS-6: Basic architecture & related blocks CAS. A, 1 h of data CAS.A with strong RFIs (the Tv station in the lower part of the band are mitigated)

  24. DS-6: T4 Phased array on concentrators Focusing the task with J.G. B.de Vaate and Laurens Bakker It could be feasible to install a tile on the focal line… …..but after an electromagnetic analysis

  25. THANK YOU

  26. SpareDiapos

  27. DS-6: Basic architecture & related blocks • A zoom shows the strong source in the center and the image artifacts. The deconvolution worked very well. Most of the source has been phased up into a single pixel at 50deg 48min 53.6s (CAS)

  28. DS-6: Basic architecture & related blocks

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