Architecture optimization and design verification of the Timepix3 and the Velopix pixel ASICs

1. Architecture optimization and design verification of the Timepix3 and the Velopix pixel ASICs 14.11.2013 Tuomas Poikela (TUCS/CERN) SV/UVM Mini workshop

2. Outline • Introduction (Pixel chip & TLM) • Architecture optimization • Transaction level model (TLM) • Integration with verification environment • Design verification • Reusing modeling framework • Testbench architecture • Assertions SV/UVM workshop T. Poikela

3. Introduction • Techniques presented here used in two pixel ASIC projects: Timepix3 and Velopix • 256x256 pixel ASICs with 55um x 55um pitch, designed using 130nm CMOS • Timepix3 has been manufactured and tested to work (characterization not fully done yet) • Velopix is still a work in progress, but the design is very well advanced SV/UVM workshop T. Poikela

4. Pixel readout chip interfaces Input interface (sensor/ discriminators) Pixel matrix (active area) Periphery TFC (reset, sync, etc.) Slow control Data outputs SV/UVM workshop T. Poikela

5. TLM notation Initiator port Bit-level interface Put-interface Target port/export Analysis- interface Components (agents, scoreboards, BFMs…) Get-interface SV/UVM workshop T. Poikela

6. Architecture optimization SV/UVM workshop T. Poikela

7. Testbench for optimization Test class (ovm_test) Configuration object Sequence library Pixel ASIC TLM DUT (ovm_component) Input agent Output agent Output data interface Discriminator interface TLM Scoreboard SV/UVM workshop T. Poikela

8. Pixel ASIC TLM Pixel ASIC TLM DUT (ovm_component) Each port specialized for packet transaction Column 0 Periphery FIFO Arbiter Column 1 Virtual router FIFO Output block Bus Column N All components modelled as ovm_components. FIFO Not all TLM ports/components shown inside the periphery. SV/UVM workshop T. Poikela

9. Transaction definition Each TLM port in TLM model specialized with TPX2PacketTransaction SV/UVM workshop T. Poikela

10. TLM Framework extends Sequence & test library Component library ChipBase BaseSeq class TestBase; Column Base ChipBase chip; BaseSeqseq; Chip0 Chip1 Monte CarloSeq Random Seq Arbiter base SuperPixelColumn Pixel Column EoCBase Token Arbiter Class Test0 extends TestBase; Class Test1 extends TestBase; PeripheryBase set_type_override( ChipBase, Chip0) set_type_override( ChipBase, Chip1) ColumnBus EoC Arbitrated set_type_override( BaseSeq, RandomSeq) PeripheryBus SV/UVM workshop T. Poikela

11. Different modeling approach (non-TLM/OVM) moduleTopLevel_tb; TopLevelSim simulation = new; initialsimulation.run(); classTopLevelSim; Chip model List of packets Pixel Matrix Monte Carlo data Packet creator Periphery Scoreboard Packet Pool (Ideally one object at top-level) Constrained Random Data generator Result extraction SV/UVM workshop T. Poikela

12. Simulation main loop • Completely untimed • style • Can use C++ as well • Seems to be 4-8 x faster • than TLM model Can add timing by using #25ns; No performance loss. SV/UVM workshop T. Poikela

13. Design verification SV/UVM workshop T. Poikela

14. RTL Verification Environment Test class (ovm_test) Configuration Pixel ASIC RTL DUT Input agent Pixel Trans-actor Output Trans- actor Conver ter Output agent Register updater Slow Control Agent TFC Agemt Virtual Sequencer Configuration registers RTL Scoreboard (hierarchical) SV/UVM workshop T. Poikela

15. Test base class Test base class Actual, derived test SV/UVM workshop T. Poikela

16. Scoreboard block diagram RTL Scoreboard (hierarchical) Black box view White box view Packet generator Control packet scoreboard Configuration registers Write Implem. Slow control Scoreboard Datapath scoreboard Checker ErrorDB PacketDB SV/UVM workshop T. Poikela

17. Configuration registers Configuration registers, ovm_object • Created in test class • Passed to components inside a config object • Each register is an ovm_object, has a coverage model • Only handful of registers but > 800 LOCs of SV (excluding drivers, macros etc.) Output block General Pixels Test pulse PLL Power pulsing Analog config + register typedefs Typedefstruct {… …} PixelReg_t; Register package SV/UVM workshop T. Poikela

18. Assertions – using macros Source: C. E. Cummings. SystemVerilog Assertions Design Tricks and SVA Bind Files. 2009. SV/UVM workshop T. Poikela

19. Assertions cont’d ERROR. Data changed 1 clock after req. No error. Data stable 1 clock before and after. ERROR. Data changed 1 clock before req. SV/UVM workshop T. Poikela

20. Scripting flow Sequence library System Verilog code Test library + verif. environment Top-level modules IUS simulation scripts -one per module IUS compilation scripts Simulator Shell Coverage regress.pl PERL script ./regress.pl -f ius_script.f -t test_list_N.t work_dir0 Master log file Simulations logs work_dir1 Run 0 log file work_dirN Test list 0 Test list N Run N log file Results SV/UVM workshop T. Poikela

21. Concluding remarks • Few use cases of SV + OVM have been presented • Modeling of a pixel chip • RTL verification: Testbench structure using OVM • Plan is to move to UVM for Velopix (and maybe change the high-level model from TLM/OVM to pure SV) • Use assertions! SV/UVM workshop T. Poikela

22. Thank you for the attention! SV/UVM workshop T. Poikela