IDPU FSW Critical Design Review F. Harvey University of California - Berkeley

1. IDPU FSW • Critical Design Review • F. Harvey • University of California - Berkeley

2. Overview • Flight Software Overview • Documentation • Development Process • Requirements • Design, Modules • Resource Summary • Schedule • Issues

3. Documentation Stored on ftp://apollo.berkeley.edu/pub/Themis: ftp://apollo.berkeley.edu/pub/Themis/Systems/Requirements ftp://apollo.berkeley.edu/pub/Themis/Systems/ICDs ftp://apollo.berkeley.edu/pub/Themis/Instruments/IDPU/FSW/Docs THM_FSW_001D_SRS (Software Requirements Specification) THM_FSW_003_CTM (Command and Telemetry)

4. Documentation • FSW Primary Documentation FSW Technical Notes

5. Documentation • FSW Reference Documentation

6. Development Process • Heritage tools • Assembler, Linker, utilities from earlier satellite efforts • Some specific DCB tests use C tools and debug equipment from Stereo. • Centralized storage • apollo.berkeley.edu/pub/THEMIS/Instruments/FSW/Code • apollo.berkeley.edu/pub/THEMIS/Instruments/FSW/Docs • Reviews • Completed Software Reqs Specification Review 4/1/04 • David King principal reviewer. Dorothy Gordon and investigators, as required.

7. Development Process • Primary Development Platforms (2) • DCBs 1 & 3(Data Controller Board), follow flight revisions • GSE Interface Board, as BAU Simulator (clocks, commands, HST) • GSE Interface Board, as test pattern generator • Rom Emulator (Tech-Tools ER3) • Toolset 1: C compiler and Rom Monitor program • Toolset 2: Heritage tools for assembly language • GSE PC & s/w for high speed data collection • 1 in Boston (h/w support), 1 in Berkeley (s/w development) • Test Platforms (2) • DCBs 2 & 4 • GSE Interface Board as BAU Simulator • ETU under test (BEB, DAP…) • GSE PC for high speed data collection • One of these becomes the IDPU Simulator for Swales

8. Deliverables • Deliverables • IDPU Simulator • Phase 1, or better, FSW • Needed at Swales to match with BAU EDU (Summer 2004) • Phase I – Board level • April-May 2004 • Phase II – Box Level • Data acquisition, SSR • PROM image, final. • Summer 2004 • Phase III – instrument level • Control external parts • Boom deployment • ESA covers, SST attenuator • June (as tests allow) • Phase IV – science optimization • Triggers, science modes • Compression • October

9. Requirements • Changes since PDR • IDPU Simulator (s/w) • When boards turned off, set enables such that _CLK lines are near ground. • For DFB (filter) channels with packet switch rates > 16 seconds, FSW to ‘arm’ the DMA channel before the switch point. • 2 virtual channels (not 1). • 4th mode, Low Power (vs Safe) • No longer need termination modes for ETC DMA channels. • FGPA version #

10. Data Collection • Data Collection • DMA Channel Controller Assigned to Each Data Source • FSW Hands Packet Addresses to Each DMA Channel Controller • Double-Buffered DMA Address to Eliminate Gaps • DMA Channels Are Sync’d to either Time or Spin-Phase • FSW Initializes Each DMA Channel for type of Synchronization • FSW writes Headers for Each Packet as it is Produced • NEW: FSW ‘arms’ very slow channels to change buffer addresses. • Data Collection Rates • Peak Input Rate of 430 KB • Preferred Length just under 4 KB for raw data packets • Peak Packet Rate of 157 Packets/sec • Performance Calculation: ~300 cycles/header, ~2.4% CPU • NEW: Basic h/w s/w interface tested in March.

11. Data Compression • Data Compression • Multiple Algorithms Available (ref. thm_fsw_901_Compression) • Huffman4 • Delta Modulation • Combined Delta Mod/Huffman • Run Length not effective on this data • Numerous Studies of Compression Algorithm Performance • Used Cluster Flight Data • Similar Instrumentation, Expected Signal Levels • Similar Data Volumes • Achieved appx 1.5 compression without being Adaptive • Needed Adaptive Behavior to Get to 1.8+ or more • Performance Studies of Non Adaptive Compressors • Huffman4x2 Algorithm 21 KB/sec • Delta Modulation Algorithm 11-14 KB/sec • Entire Memory Compressed in 1-2 hours

12. Science Telemetry • Science Telemetry • Packets Selected are Handed to DCB High Speed TLM DMA • Address of the 4K Block and Length in Bytes • FSW receives Interrupt when the Address Pointers Swap • FSW has 1 Packet Time to refresh DMA Address Pointer • Packet Rate Determined by Packet Length • If Packets are 2-4KB in length, then at 2Mbps transfer rate, FSW outputs ~50 to 100 packets per sec. • If Packets are Compressed, then FSW may find very short packets. • Packet Mixing • VC2 for quicklook data, VC3 for stored data.

13. Triggers • Trigger Calculations Using In Situ Data • FSW Continuously Samples Science Data in SSR (e.g. ESA/SST Peak Flux, DFB V1-V6 Voltages, FGM Bx-Bz) • Evaluates Data Quality at 8 Hz • Calculates Quality using 8 Selectable Functions • Result Values 0-255 • Specific Functions are TBD (Phase IV) • Conjunction Prioritization • FOT will uplink Predicted Conjunction Times • FSW increases Quality Value near Conjunction • FSW decreases Quality Value near downlink • Conjunction Duration and Bias are Commandable

14. Resources • PROM/EEPROM • PROM Functions • EEPROM Load • Uplink Support • L&EO Functions • EEPROM/Uplink • One-Time Events • Test Programs • Initialization Params • Science Upgrades • RESOURCE USAGE • 72% PROM • 33% RAM • 50% EEPROM • 36.5% CPU

15. Schedule FSW ETU Schedule FSW ETU Phase I Board Lvl Development 4/9/04 FSW ETU Phase I Test 5/11/04 FSW ETU Phase II Box Lvl Development 6/8/04 FSW ETU Phase II Test 6/15/04 FSW ETU Phase III Inst Lvl Development 6/22/04 FSW ETU Phase III Verification w Sims 7/6/04 FSW FLT PROM FINAL 7/6/04 FSW FLIGHT Schedule FSW FLT SPEC MODS FSW FLT Development/Test FSW FLT Phase IV Science Development FSW FLT Phase IV Test 10/12/04