PSPICE 计算机仿真

1. PSPICE计算机仿真 Simulation Program with Integrated Circuit Emphasis

2. CH7 THE STEP RESPONSE AND SWITCHES 阶跃响应

3. 7.1 Simple step response

4. Fig. 69

5. Example 11 • a) The switch in the circuit shown in Fig. 69 is closed at t=0. At the instant the switch is closed, the initial current in the 10 mH inductor is 90 mA, and the voltage across the capacitor is 10 V.

6. Fig. 69 also shows the references for these initial conditions. Make a preliminary analysis of the step response, and calculate the maximum value of Vc and the time at which it occurs.

7. b) Create a PSpice schematic, perform transient analysis, and plot Vc versus t from 0 to 3000 µs. • c) Compare the PSpice solution with the preliminary analysis.

8. Solution a) • From the solution of Example 10, we already know that the response is underdamped. • Furthermore, we know that the damped period is 897.60 µs, and that

9. The step-response solution for Vc takes the form

10. The initial values of Vc and dVc/dt are the same as in Example 10, and the final value is 21 V. Hence B’1=-31 V and B’2=2 V, so

11. The maximum value of Vc is 41.22 V at 419.32 µs.

12. Solution b) • In Fig. 71, we used two cursors this time, and moved the second cursor by holding down the Shift key while using the left and right arrow keys. The cursors allow you to read the values of Vc (max) and Td directly from the Probe plot.

13. Fig. 70 schematics

14. Fig. 71 probe

15. Solution c) • The output of the PSpice analysis yields

16. 7.2 Piecewise Linear Sources (分段线性电源) • Example 12 illustrates the use of the piecewise linear source for modeling the switching that takes place in a transient analysis problem.

17. Example 12 • The circuit shown in Fig. 72 has been in operation for a long time. At t=0, the 80 V source drops instantaneously to 20 V. Construct a PSpice schematic, using a PWL source, to model this circuit. The results of the analysis should be a plot of Vo (t) versus t.

18. Solution

19. Fig. 73 Ex12_ddb

20. Fig. 74 Schematic

21. 注意V2正负极 • V2属性 (Fig. 75)

22. Fig. 75 PWL Property Editor

23. Fig. 75a Simulation Profile

24. Fig. 76 Probe

25. Results • The Probe plot in Fig. 76, which uses the cursors to determine the output voltage at t=40 ms and t=80 ms, yields the following results: t Vo(t) 0 64 40 33.698 (书上:33.654) 80 22.489 (书上:22.498)

26. Furthermore, you can see from the Probe plot that Vo(t) approaches 16 V as t approaches ∞.

27. 7.3 Realistic Switches (实际开关) • We illustrate the use of the normally-opened switch in Example 13 to examine the effect of nonzero switch resistance on the step response of the RLC circuit.

28. Fig. 69

29. Example 13 • Use PSpice to model the circuit shown in Fig. 69, with some modifications. • Assume that the voltage source is the same as that used in Example 10, and use the same values in specifying transients analysis. • But assume that the resistance of the switch in the ON position is 10 Ω.

30. Then generate a plot of Vc versus t. Compare the results here with those in Example 10.

31. Fig. 77 Schematic

32. Components • EVAL/Sw_tClose

33. Fig. 78 Property

34. Fig. 79 Probe