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CALICE TPAC1.1: Power Plan

This document provides a detailed overview of the metal layers and power planning strategies used in advanced circuit design. It highlights key aspects such as missing horizontal links between sub-arrays, various voltage supply points (VDD/VSS), and various signal biases. The focus is on the identification of specific pixel rows and columns within the layout, as well as issues related to SRAM and guard voltages. Attention is drawn to necessary revisions and checks required in the design to ensure optimal performance.

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CALICE TPAC1.1: Power Plan

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  1. Metal 2 Metal 3 Metal 4 Metal 5 Metal 6 CALICE TPAC1.1: Power Plan 42 pix 84 pix (Top Level)

  2. 1.1 VDD1V8pix & VSS:Gpix

  3. 1.1 (new mesh) VDD1V8aco & VSS:Gaco

  4. 1.1 VDD1V8dco & VSS:Gdco

  5. 1.1 (attn!) VDD1V8mso & VSS:Gmso Horizontal links between sub-arrays missing! TO DO

  6. 1.1 VDD1V8sram & VSS:Gsram

  7. 1.1 VGUARD (not yet used)

  8. 1.1 Vth(+/-) & Vcasc(s) Vth12 Vth34 Vcascs, Vbiases

  9. 1.1 VDD1V8dig & VSS:Gdig

  10. VDDO & VSSO (3.3v max)

  11. VDD2V5dig (=3.3v for SRAM WrEn) 1.1 (review)

  12. 1 1 2 2 preShape BTBTTB preShape BTBTTB preShape BTBTTB preShape BTBTTB Col 01 Col 00 Col 11 Col 10 Pixel Identification Row 0 Row 1 Row 2 etc [GRAY] Row 83 0,1,2,3 … 42 0,1,2,3 … 42 0,1,2,3 … 42 0,1,2,3 … 42 Row 84 Row 85 Row 86 etc [GRAY] Row 167 0,1,2,3 … 42 0,1,2,3 … 42 0,1,2,3 … 42 0,1,2,3 … 42

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