LLRF-ATCA LOW LEVEL APPLICATIONS

1. LLRF-ATCA LOW LEVEL APPLICATIONS Tomasz Czarski Maciej Linczuk Institute of Electronic Systems, WUT, Warsaw

2. AGENDA • Introduction • Requirements • Concept and design • Algorithms • ATCA architecture • Applications • Interfaces • Experimental results • Development proposal • Conclusions

3. Low Level Applications introduction The part of Software adjacent to the Controller responsible for the arrangement of the control algorithms • TASKS: • Implementation of the procedures and data processing to provide Control Data and parameters for the Controller • Monitoring and Exception Handling for safety requirements Control a lgor i thms a r r a n g i n g field control managing e x e c u t i o n LOW & HIGH LEVEL APPLICATIONS RF SYSTEM CONTROLLER DOOCS

4. Outline of the LLRF control structure RF SYSTEM Tunercontrol Vector Modulator MULTI–CAVITYMODULE Klystron forward Beam detector forward reflected probes Multi–channel Down-Converter DAC Multi – channel ADC IQ C T R L Controller Core Exception Detection and Handling Control Data & Parameters Data Acquisition Memory Control Data& Parameters I/O Data COMMUNICATION C O N T R O L LOW LEVELAPPLICATIONS SYSTEM MODEL IDENTIFICATION MONITORING DATA Preprocessing HIGH LEVEL APLICATIONTS D O O C S

5. Requirements • Functional modes • Control - provides Control Data between pulses • Simulation – for testing • VM offset compensation – on request • Vector Sum calibration – always for new operation condition • Performance • Control Data meet requirements for cavity field control: • filling: energy efficiency = stored/expanded energy • optimal target ~74% for 0.5 ms filling • flattop: field stability : 10-5 in amplitude, 0.01° in phase • Reliability • robust algorithms • Usability • user friendly, context DOOCS GUI, on/off button operability • Interface • input/outputs to Controller, High Level Applications and DOOCS • Safety • monitoring: gradient, klystron power, quench detection • exception handling: controller off, beam off

6. The LLA Concept & Design DATA p r e - p r o c e s s i n g Controller Cavity I/Q Detection Calibration Estimation Klystron I/Q Detection Estimation Beam Estimation Controller Estimation DOOCS Cavity gradient Vector Sum Estimation Input/output DATA Monitoring C O N T R O L Model Structure • Klystron feature • Detuning • Half-bandwidth • Coupling factors • VM offset Set-Point Loop gain DAQ Memory Parameters Inverse Model SystemIdentification Feed-Forward Set-Point Gain Coefficients Simulation Error out + – + CORRECTOR Feed-back ADC I/Q DETECTOR Vector Sum CALIBRATOR IQ DAC ~IF CONTROLLER CORE

7. System Model for Identification Algorithm Internal CAVITY model Klystron Output Cavity phasor { vik+1=Aik·vik + Bi·uk } Aik= 1-T(ωi1/2)k + i·T∆ωik klystron phasor {vik} uk = Dk·xk Ei uk N - channels xk ∑ Multi-Cavity model Calibration Ei·Ci= 1 vk+1=Ak·vk + B·uk Ak= 1-T(ω1/2)k + i·T∆ωk Controller phasor vk+1=Ak·vk + Fk·xk Fk= B·Dk Corrector Vector Sum feedback phasor error phasor Ci + – + {vik} ∑ Gk vk FFk SPk Gk Ci Calibrator

8. MULTI - CAVITY RF SYSTEM CONTROLLER - FPGA CONTROLLER Core DAQ MEMORY CONTROL TABLES C O M M U N I C A T I O N PRE- PROCESSING CONTROL DATA SYSTEM MODEL IDENTIFICATION LLA - DSP ATCA based implementation of LLA

9. Set of Low Level Applications

10. Interfaces High Level Applications & DOOCS Operation mode Control setting: pulse, field, gain Beam parameters Cavity gradient Monitoring data Exception signals Low Level Applications ADC data: klystron out cavity probe Vector Sum Controller out Feed-Forward Set-Point Corrector Gain Calibration coefficients Simulation CONTROLLER

11. System Identification - Experimental resultsACC1 – cavity 4 (gradient ~11 MV/m)

12. System Identification - ACC1 Model verification

13. Development activity proposal • Tasks realization • Low Level Applications • Data pre-processing • System Model Identification • Control Data & Parameters • Monitoring • Integration with „Communication” • LLA Simulation and integration with controller firmware simulation Schedule for 2008-2009(tightly integrated with controller design)‏ • Development of the existing algorithm - 12 m. • Tests in simulation - 15 m. (in the background) • Operability development – 6 m. • DOOCS server integration – 6 m. • DSP implementation – 12 m. • Development team • ISE Employees • Tomasz Czarski, MSc • Maciej Linczuk, PhD • Wojciech Zabolotny, PhD • Krzysztof Pozniak, PhD • IPJ Employees • Jaroslaw Szewinski, MSc • DESY Employees/ISE PhD stud. • Waldemar Koprek, MSc • Piotr Pucyk, MSc • DMCS PhD Student • Wojciech Jałmużna, MSc

14. CONCLUSIONS • The Low Level Applications algorithms has been verified experimentally for feed-forward and feedback modes • ATCA carrier board with AMC modules is scaleable and flexible platform for implementation of the control algorithms with possible upgrade of future development • The Low Level Applications strongly influence the architecture of the Controller and Communication structure and shares the same hardware platform • The integrated design – packages Controller and LLA, managing by the unified team, without any division, is the only reasonable solution for the LLRF – XFEL development