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Flash Memory from SSD Design Viewpoint

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90 diapositives · 1.9K Views · Mar 16, 2012

Flash Memory from SSD Design Viewpoint. Sungjoo Yoo Embedded System Architecture Lab. Agenda. NAND Flash memory Internal operations and reliability Flash memory organization and operations Read, program, and erase ECC (error correction code) Wear leveling, etc.

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  1. Flash Memoryfrom SSD Design Viewpoint Sungjoo Yoo Embedded System Architecture Lab. ESA, POSTECH, 2010

  2. Agenda • NAND Flash memory • Internal operations and reliability • Flash memory organization and operations • Read, program, and erase • ECC (error correction code) • Wear leveling, etc. ESA, POSTECH, 2010

  3. Context: SSD in Notebook and PDA • SSD Benefits • High performance, low power, and reliability 10 Flash memory chips ESA, POSTECH, 2010

  4. An Example: Intel SSD • Especially good for random accesses w.r.t. HDD ESA, POSTECH, 2010

  5. [Source: J. Lee, 2007] NOR vs. NAND Summary • NOR Flash • Random, direct access interface • Fast random reads • Slow erase and write • Mainly for code storage • NAND Flash • Block I/O access • Higher density, lower cost • Better performance for erase and write • Mainly for (sequential) data storage ESA, POSTECH, 2010

  6. [Source: Samsung, 2000] Area Efficiency • Metal contacts in NOR cell are the limiting factor: 2.5X difference in area/cell ESA, POSTECH, 2010

  7. NAND Flash Memory Circuit [A 113mm² 32Gb 3b/cell NAND Flash Memory]

  8. [Source: Samsung, 2000] NAND Program & Erase ESA, POSTECH, 2010

  9. [Suh, 1995] Bias Conditions for Erase, Program, and Read

  10. [Source: Z. Wu, 2007] SLC vs. MLC • SLC (single level cell) vs. MLC MLC SLC probability 10 00 01 0 11 1 voltage Vth • Fast, less error • Low bit density • Slow, more error • High bit density + ECC (error correction code) E.g., RS, LDPC, BCH, … E.g., 4bit ECC for 512B ESA, POSTECH, 2010

  11. - Achieving typical 2.3MB/s program performance with an ISPP scheme - lowering the pate programming current using self-boosting of program inhibit voltages A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme ISPP conventional Vpgm Vpgm time time

  12. - Achieving typical 2.3MB/s program performance with an ISPP scheme - lowering the pate programming current using self-boosting of program inhibit voltages A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme 0.6V Distribution of program cycles number in a chip, The ISPP device has the narrowest distribution Programmed cell with Vth distribution of device with ISPP and 2 devices with fixed Vpgm pulses

  13. - Achieving typical 2.3MB/s program performance with an ISPP scheme - lowering the pate programming current using self-boosting of program inhibit voltages A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme Convectional method

  14. Circuits and algorithms which result in an approximately 30% increase in program throughput compared to the conventional scheme A 48nm 32Gb 8-Level NAND Flash Memory with 5.5MB/s Program Throughput

  15. (2008) • Three major parasitic effects • Background pattern dependency (BDP) • Noise • Cell-to-Cell interference • Proposed solution : • Reduce the number of neighbour cells • Reduce the Vth shift A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

  16. Features of 32Gb 3b/cell (D3) NAND flash memory with sub-35nm CMOS process (This has reduced cost and increased density compared to conventional chips) A 113mm² 32Gb 3b/cell NAND Flash Memory

  17. NAND structure and Operation reading programming

  18. [Shibata, 2008] Floating Gate Coupling Effects

  19. - Programming method suppressing the floating gate coupling effect and making the narrow Vth distribution for 16LC A 70nm 16Gb 16-Level-Cell NAND flash Memory

  20. - Programming method suppressing the floating gate coupling effect and making the narrow Vth distribution for 16LC A 70nm 16Gb 16-Level-Cell NAND flash Memory Vth distribution transition of 16LC Comparison of Vth distribution

  21. Features of 32Gb 3b/cell (D3) NAND flash memory with sub-35nm CMOS process (This has reduced cost and increased density compared to conventional chips) A 5.6MB/s 64Gb 4b/Cell NAND Flash Memory in 43nm CMOS

  22. Flash Reliability

  23. [Source: Samsung, 2000] NAND Flash Lifetime • # of erase operations is limited due to degradation  wear leveling & ECC are needed! ESA, POSTECH, 2010

  24. representing raw error data from multi-level-cell devices from four manufacturers,identifying the root-cause mechanisms,and estimating the resulting uncorrectable bit error rate(UBER) Bit Error Rate in NAND Flash Memories

  25. representing raw error data from multi-level-cell devices from four manufacturers,identifying the root-cause mechanisms,and estimating the resulting uncorrectable bit error rate(UBER) Bit Error Rate in NAND Flash Memories Detrapping SILC

  26. representing raw error data from multi-level-cell devices from four manufacturers,identifying the root-cause mechanisms,and estimating the resulting uncorrectable bit error rate(UBER) Bit Error Rate in NAND Flash Memories

  27. representing raw error data from multi-level-cell devices from four manufacturers,identifying the root-cause mechanisms,and estimating the resulting uncorrectable bit error rate(UBER) Bit Error Rate in NAND Flash Memories

  28. Column-Dependent Errors Redundant bitlines! Redundant bitlines? [Swenson, 2009]

  29. Agenda • NAND Flash memory • Program and reliability • Flash memory organization and operations • Read, program, and erase • ECC (error correction code) • Wear leveling, etc. ESA, POSTECH, 2010

  30. [Source: J. Lee, 2007] Flash Operations • Operations • Read • Write or Program • Changes a desired state from 1 to 0 • Erase • Changes all the states from 0 to 1 • Unit • Page • Read/Write unit (in NAND) • Block • Erase unit write erase ESA, POSTECH, 2010

  31. [Source: Micron, 2006] NAND Flash Architecture: 2Gb Case tR tPROG ESA, POSTECH, 2010

  32. [Source: Micron, 2007e] Small vs. Large Block ESA, POSTECH, 2010

  33. [Source: Micron, 2007e] Performance Comparison Small block 12.65MB/s for read 2.33MB/s for program 33ns*2K = 66us tR = 15us tPROG = 200us Large block 16.13MB/s for read 5.20MB/s for program tR = 25us tPROG = 300us Runtime reduction! Note: The same erase time per block! ESA, POSTECH, 2010

  34. [Source: Micron, 2006] Read Operation 25us Data ESA, POSTECH, 2010

  35. [Source: Micron, 2006] Pin Description ESA, POSTECH, 2010

  36. [Source: Micron, 2006] Commands & I/O Multiplexing ESA, POSTECH, 2010

  37. [Source: Micron, 2006] Erase Operation ESA, POSTECH, 2010

  38. [Source: Micron, 2006] Program Operation ESA, POSTECH, 2010

  39. [Source: Micron, 2006] Program with Random Data Input • Often used for partial page program ESA, POSTECH, 2010

  40. [Source: Micron, 2006] Page Storage Methods ESA, POSTECH, 2010

  41. [Source: Micron, 2006] Read Operation (Revisited) ESA, POSTECH, 2010

  42. [Source: Micron, 2006] Page Read Cache Mode ESA, POSTECH, 2010

  43. [Source: Micron, 2007] Comparison between Normal Read and Page Mode Cache Read ESA, POSTECH, 2010

  44. [Source: Micron, 2006] Commands & I/O Multiplexing ESA, POSTECH, 2010

  45. [Source: Micron, 2007] Page Read Cache Mode Operation ESA, POSTECH, 2010

  46. [Source: Micron, 2007] Performance Comparison ESA, POSTECH, 2010

  47. [Source: Micron, 2006] Program Page Cache Mode ESA, POSTECH, 2010

  48. [Source: Micron, 2006] Overlapping Program Data Cycles and tPROG ESA, POSTECH, 2010

  49. [Source: Micron, 2006] Commands & I/O Multiplexing ESA, POSTECH, 2010

  50. [Source: Micron, 2007b] Program Page Cache Mode Operation ESA, POSTECH, 2010