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CPU Architecture

CPU Architecture. cs2503. Vocabulary. Cache – temporary storage locations available for rapid access. Common Sections of a CPU die. Clock - reset Cores L3 Cache memory Core control interface Integrated memory control unit Integrated GPU. Common Section of a CPU die.

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CPU Architecture

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  1. CPU Architecture cs2503

  2. Vocabulary • Cache – temporary storage locations available for rapid access.

  3. Common Sections of a CPU die • Clock - reset • Cores • L3 Cache memory • Core control interface • Integrated memory control unit • Integrated GPU

  4. Common Section of a CPU die • Core control interface • BSB connects cores to the off-core, on die cache (L3) • FSB connects the cores and L3 cache to the on chip Integrated Memory Control Unit. (once handled by the Northbridge) • Memory bus connects the IMCU to main memory

  5. Core Sections • Registers (L0) • Cache (L1 and L2) • Functional Control Units • Core Bus • BSB

  6. Core Sections • Registers – Static RAM • Instruction • Integer • Floating point

  7. Core Sections • L1 and L2 cache (Static Ram)

  8. Core Sections • Functional Units, examples: • Arithmetic-Logical unit • Integer unit • Address unit • Floating point unit • Branch unit • Instruction unit • Input/output management unit

  9. Core Sections • Core bus connecting the functional units and cache • BSB – back-side bus connection between the core and off-core cache.

  10. :

  11. Common Micro-Processors • Intel and Intel clones • AMD • Power PC – By Motorola used by Apple & IBM. • Sparc – Sun Microsystems. • MIPS - SGI • Alpha – Compaq/DEC

  12. 32 vs 64 bit Architecture • 4-billion addressable bytes vs a bunch more.

  13. Processor History • The DEC Alpha was the first true 64 bit architecture used in the Cray T3E in 1995.

  14. CPU Performance Factors • CPU Clock speed. • Memory/data bus width – anywhere from 8 to 256 bits wide. • Memory/data bus speed – measured in units similar to clock speed. • The number of Functional Units. • Pipelining of Functional Units. • Chip cache size. • Number of registers • Instruction Scheduling • Threading • Number of cores

  15. Example • Q: How is it possible for a 3.2 GHz processor to be only half as fast as a 1.6 GHz processor for some tasks? • A: The 1.6GHz processor may have a wider and faster data bus, and more on board cache. It may also be able to do multiple tasks simultaneously.

  16. Cache Summary • L0 – on core register cache, ~128 per category • L1 – on core cache, ~32KB • L2 – on core cache, ~256KB • L3 – off core on die cache, 6MB (values are from intel i5 sandy bridge)

  17. Pipelining the laundry

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