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Dr. Eric Bogatin , Signal Integrity Evangelist, Teledyne LeCroy

Essentials of Jitter Session 1 Intro to Jitter: What is Jitter, and Why is it Important to Characterize?. Dr. Eric Bogatin , Signal Integrity Evangelist, Teledyne LeCroy Dr. Alan Blankman , Product Manager, Teledyne LeCroy.

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Dr. Eric Bogatin , Signal Integrity Evangelist, Teledyne LeCroy

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  1. Essentials of JitterSession 1Intro to Jitter: What is Jitter, andWhy is it Important to Characterize? Dr. Eric Bogatin, Signal Integrity Evangelist, Teledyne LeCroy Dr. Alan Blankman, Product Manager, Teledyne LeCroy

  2. Note – this pptx file includes some custom animation, and should be “presentation mode”

  3. Jitter Matters. Yet it is Misunderstood. Total Jitter - Tj Deterministic Jitter - Dj Random Jitter - Rj • Industry knowledge: Highly variable • In practice, definition is also variable • Misconceptions: Plenty • E.g., Pk-pk vs. RMS vs. “Dual-Dirac” • Results: Setup-dependent • Scope specs & setup • Data itself • Jitter model, distribution, CDR, etc • Our goal: Educate! Data Dependent Jitter - DDj Intersymbol interference - ISI Duty Cycle Distortion - DCD Periodic Jitter - Pj Bounded Uncorrelated Jitter - BUJ Unbounded Jitter Correlated Jitter Uncorrelated Jitter Dual-Dirac Model Jitter PDF Jitter CDF Bathtub curve Jitter Spectrum Jitter Track Jitter Histogram Jitter Transfer Function PLL Transfer Function

  4. Jitter 101 • Three 45-minute sessions, with questions/breaks:

  5. Why Measure Jitter? The goal of your serial data design: Transmit data without incurring (many) bit errors … Analyzing jitter is important for achieving first-pass success A typical channel consists of multiple structuresand jitter sources Source: PCI Express 2.0 Electrical Overview Presentation (w/revised text)

  6. Fundamental Truth: Jitter  Bit Errors • Timing jitter and noise cause edges to arrive early/late compared to an expected arrival time Wrong edge timing  Incorrect latching  Bit error • Examples: When latching edge at time of vertical cursor, bit = 0 Edge is too late! Bit is low, latched as “0” Crossing detection level Doesn’t cross threshhold! Latch (strobe) time

  7. It’s all about Bit Error Rate/Ratio (BER) • Specifications aim for extremely low BER • The BER of a channel is important: Not meeting BER requirements can be costly • “Quality of Service” contractual requirements • Datasheet specifications for clock and serdes Jitter

  8. Planning for Jitter • Electrical specs include budget & limits… USB30:

  9. Definition of Timing Jitter • Settle on this measurement-based definition: Timing jitter is the result of an analysis of Time Interval Error (TIE) measurements • TIE results can be a histogrammed, tracked, FFT’d, separated, decomposed, averaged, etc, etc, etc.

  10. It all starts with TIE Time Interval Error (TIE): Measured Arrival Time of an edge – ExpectedArrival Time for the edge Time Interval Error for the edge • TIE describes how early or late an edge arrives compared to its expected arrival time • Multi-step process to make the measurement Signal is late

  11. Determination of Measured Arrival Times • What gets done on a real-time digital oscilloscope: • Determine the crossing times Sample points Interpolated Edge arrival time Next Step: find the expected arrival time

  12. Determination of Expected Arrival Times • Two scenarios relating to signaling methods: • Reference clock and/or strobe is transmitted • e.g., DDR, clock/strobe signal latches bit • No clock signal is transmitted • e.g., USB: clock and data recovery (CDR) circuit.

  13. Determination of Expected Arrival TimesScenario 1: When using a reference clock • Expected arrival times of the data edges = measured arrival times of the clock signal’s edges Ref Clock

  14. Determination of Expected Arrival TimesScenario 2: Data only, no clock signal • Use the data to determine the underlying clock • Software Clock and Data Recovery (CDR) algorithm finds bit rate • Assumption: The correct bit rate minimizes the average TIE of the entire waveform

  15. Software CDR Steps Step 1: Determine underlying bit rate Step 2: Determine expected arrival times

  16. Software CDR Algorithm Step 1: Determine the Bit Rate • Bit rate is determined via analysis of edge times • Example algorithm: • Histogram delta-T between successive rising edges • Analyze to determine first-pass bit rate • Create scatterplot of edge time vs. cumulative # UI’s • Find slope of scatterplot Histogram of time between successive rising edges 2 UI 4 UI 6 UI 8 UI 200 ps 400 ps 600 ps 800 ps

  17. With ISI, it is a Bit Trickier Clock is still recoverable via histogram Histogram of time between successive rising edges Clock is no longer recoverable Equalization needed to open eye

  18. Software CDR Challenges • Algorithms break down when eye is closed • CDRs are sensitive to long runs of 1 and 0 bits • Signaling standards avoid this: • 8b/10b, 64b/66b: “scrambling” • Convert pattern to a different pattern with a more desirable transition density

  19. Software CDR AlgorithmStep 2: Determine Expected Arrival Times • Method 1: Create a list using a constant UI time • Nominal UI Time is 1/Bitrate • i.e., assume that the underlying clock is “perfect” • Method 2: Allow the UI time to vary using a Phase-Locked Loop (PLL) • Corrects for low-frequency jitter or “wander” in underlying clock • Oscilloscopes let you select from various PLL types

  20. Software CDR Block Diagram • The SW CDR allows the expected arrival timesto vary from the nominal interval of 1/Bitrate • Oscilloscope emulates the PLL in a receiver • Use a PLL that best matches your receiver

  21. Finally, Determination of TIE Values • Expected arrival times is essentially a clock • Starting phase hasn’t been determined yet Nom. UI Time = 1/Bitrate Early!! Late!! Early Late Early

  22. PLL & Jitter Transfer Functions H J J = 1 - H

  23. TIE Measurement Complete! • Now have a list of TIE values, one for each edge • This is the data set to be used for all jitter analysis • Pk-Pk, sdev, histogram analysis • Further analysis requires creation of a TIE Track • Create a waveform out of the TIE measurements • Shows how the TIE values change in the same timebase as the source signal.

  24. Creating a TIE Track Waveform • This gives our TIE measurements a timebase, and facilitates further analysis Interpolate early late TIE value

  25. PLL tracks out LF Jitter, or “Wander” • Here’s a waveform that has slowly varying jitter • Goal of the PLL is to track out low-frequency jitter • Let’s look at some TIE measurements & TIE Tracks

  26. Simulation of Four Kinds of Jitter Periodic Jitter Intersymbol Interference Random Jitter Duty Cycle Distortion

  27. Take-Away: Getting the most out of TIE • Look at TIE measurements in different ways: • Your scope may/may have the TIE meas standard • Could depend on SW optioning • TIE is performed “under the hood”

  28. Is it “Correct” to use Pk-Pk? • Peak-Peak is not a well-defined statistic • Random jitter is unbounded • Expected Peak-Peak grows as you increasepopulation* *measured pk-pk of a sample is random: “unrepresentative” outliers happen Expectedpk-pk

  29. Is it “Correct” to Use RMS? • RMS isn’t meaningful if the jitter distribution isn’t Gaussian

  30. Session 1 Summary • Measuring jitter is important • Jitter causes bit errors, and bit errors are bad • Specifications define jitter budget & methodology • At its core, jitter is the variation in TIE TIE = Measured Arrival time – Expected Arrival time • Jitter distributions can be complicated, and not easily summarized by RMS or pk-pk values

  31. Any Questions?

  32. Essentials of JitterSession 2Introduction to Jitter Decomposition: The Components of Jitter Dr. Eric Bogatin, Signal Integrity Evangelist, Teledyne LeCroy Dr. Alan Blankman, Product Manager, Teledyne LeCroy

  33. Session 1 Quick Recap • Measuring jitter is important • Jitter causes bit errors, and bit errors are bad • Specifications define jitter budget & methodology • At its core, jitter is the variation in TIE TIE = Measured Arrival time – Expected Arrival time • Jitter distributions can be complicated, and not easily summarized by RMS or pk-pk values

  34. Session 2 Agenda • Session 1 recap • Clock signals vs. data signals: different signals, different analysis requirements • Types of jitter on NRZ serial data waveforms • Descriptions and demonstrations • Intro to the Dual-Dirac jitter model

  35. Clock Jitter vs. Data Jitter • Techniques used for each are often different • Clock signals are…. Clocks: • No data-dependent jitter, Gaussian jitter distribution • Focus has been on measurement of period, “Pj” & “Rj” • Data signals are complicated: • Jitter depends on the data, not just on the channel • Focus is on the side-effects of jitter: BER

  36. Jitter Analysis of an NRZ Data Signal

  37. The Components of Jitter • Variety of jitter types and jitter aggressors • Fairly large alphabet soup… Total Jitter - Tj Random Jitter - Rj Deterministic Jitter - Dj Data Dependent Jitter - DDj (Un)Bounded Jitter Intersymbol Interference - ISI Duty Cycle Distortion - DCD (Un)Correlated Jitter Periodic Jitter - Pj

  38. Simulation of Four Kinds of Jitter Periodic Jitter Intersymbol Interference Random Jitter Duty Cycle Distortion

  39. InterSymbol Interference (ISI) Basics • Signature: Jitter on an edge function of bit history • TIE Track repeats for a repeating pattern (e.g., PRBS7) • Bounded. And depends on data • Causes: • Reflections change the shape of an edge • Limited channel bandwidth • Know the single bit response of your channel

  40. Further Diagnosing ISI (described by S-parameter matrix) 200 psec UI ISI “echoes of bits past”

  41. Simulation of ISI

  42. Duty Cycle Distortion (DCD) Basics • Signature: two states in TIE Track and histogram • Measures difference in bit width for 0 and 1 bits • Bounded. • Caused by: • Variation in crossing level and/or shift in signal’s offset

  43. Periodic Jitter Basics • Signature: pks in spectrum, bowl-shape histogram • Bounded. • Called Pj; pure sinusoidal would be SJ • Caused by: • Coupling in of other periodic signals in system • Power supply switching frequency

  44. Understanding Random Jitter • Signature: Gaussian tails on jitter histogram • Unbounded…. Gaussian • Causes: • Thermal noise, shot noise, flicker noise • Random variations in otherwise uniform structures • Deterministic jitter contributors create an overall distribution with Gaussian tails.

  45. Understanding Random Jitter • Random jitter grows without bound, and eventually closes the eye • Take-away: Peak-to-peak is onlymeaningful for a givensample size Expectedpk-pk

  46. Histogram Growth Source: JitterTime Consulting

  47. Simulation of Random Jitter

  48. “Other” Jitter • Uncorrelated to the pattern… • Not Gaussian, not periodic… OBUJ • Other Bounded Uncorrelated Jitter • Crosstalk / interference • Interference translates into jitter • Potentially broadband; spectral noise floor rises: w/XTALK

  49. Sources of OBUJ • Crosstalk from non-repeating data (e.g., live traffic) • High rate frequency modulation on Pj component • Power supply switching noise • EMI radiation • Simultaneous-switching noise

  50. Putting it together: Overall Jitter Distribution

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