332:578 Deep Submicron VLSI Design Lecture 8 Design Margin

1. 332:578 Deep SubmicronVLSI DesignLecture 8 Design Margin David Harris and Mike Bushnell Harvey Mudd College and Rutgers University Spring 2005

2. Outline • Supply Voltage • Temperature • Process Variation • Design Corners • Matching • Delay Tracking • Summary Material from: CMOS VLSI Design By Neil E. Weste and David Harris Deep Submicron VLSI Des. Lec. 8

3. Distributions • Model design variations as uniform (normal) Gaussian distributions Deep Submicron VLSI Des. Lec. 8

4. Uniform Distribution • Specified with half-range • Accept variations all over the entire half-range • Example: Specify VDD at 1.2V +/- 10% Deep Submicron VLSI Des. Lec. 8

5. Normal Distribution • Specify with standard deviation s • Retain parts with 3s distribution – • Means 0.26% of parts rejected • Retain parts with 2s distribution – • Means 4.56% of parts rejected • Retain parts with 1s distribution – • Means 31.74% of parts rejected • 2s or 3s is common • Designers moving to statistical, not worst-case, design Deep Submicron VLSI Des. Lec. 8

6. Temperature • As T rises, ID decreases • Transistor junction T = Ambient T + T due to package power dissipation • Determined by PTOTALand package Thermal R • Verify commercial parts for 110 ºC ≤ TJUNCTION≤ 125 ºC Deep Submicron VLSI Des. Lec. 8

7. Process Variation • In film thickness, lateral dimensions, dopings • Measured: • From wafer to wafer • From die to die – inter-die • Across die – intra-die or process tilt Deep Submicron VLSI Des. Lec. 8

8. Important Device Variations • Channel length L • Photolithography proximity effects • Optics deviations • Plasma etch dependencies • Oxide thickness tox • Well-controlled -- only significant between wafers • Threshold voltageVt • Varying dopings • Annealing effects • Mobile Q in gate oxide • Discrete dopant variations (few dopant atoms in transistors) Deep Submicron VLSI Des. Lec. 8

9. Interconnect Variations • Line width and line spacing • Photolithography • Etching proximity effects • Metal and dielectric thickness • Chemical Mechanical Polishing • Contact resistance • Contact dimensions • Etch and clean steps Deep Submicron VLSI Des. Lec. 8

10. Design Corners • Design or Process Corners = Processing + Environmental Variations • Box surrounding guaranteed circuit performance Deep Submicron VLSI Des. Lec. 8

11. Process Corners • F = Fast, T = Typical, S = Slow • Corner specified with 5 letters for: • nMOS, pMOS, Wire, VDD, T • Corner specified with 4 letters for: • nMOS, pMOS, VDD, T • Corner specified with 3 letters for: • nMOS, pMOS, environment • Corner specified with 2 letters for: • nMOS, pMOS • Circuits most apt to fail at Design Space Corners • Must be simulated at all corners to guarantee operation Deep Submicron VLSI Des. Lec. 8

12. Design Corner Checks Deep Submicron VLSI Des. Lec. 8

13. Environmental Corners Deep Submicron VLSI Des. Lec. 8

14. Matching • Must frequently have pairs of transistors with closely-matched electrical parameters • Sense amplifier – offset V depends on matching • Analog circuit differential pairs • Clock tree – clock skew depends on mismatch • Mismatch due to: • Systematic variability • Example – ion implanter gives different dose to different chip parts • Can be modeled and nulled out • Uncertainty • Source unknown, random, or too costly to model Deep Submicron VLSI Des. Lec. 8

15. Controlling Variability • Vt variations scale with: • Device parameters depend on: • Size • Orientation • Nearby polysilicon density • Build identical, large transistors oriented in same direction • Surround transistor with consistent poly pattern • Vt variations due mainly to statistical fluctuations in # dopant atoms Deep Submicron VLSI Des. Lec. 8

16. Matching Problems • Systematic • Factors that can be modeled & simulated at design time (wires of different lengths) • Random • Most process variations in L, Vt, or interconnect • Drift • T – change slowly with time, compared to f • Null out by compensation circuits • Jitter • Happens at f comparable to system clock – cannot be eliminated through feedback Deep Submicron VLSI Des. Lec. 8

17. Delay Tracking • Best way is to replicate gates being matched • Example: • Use replica bit lines in static RAM to decide when sense amp. Should fire • Any mismatch in wire, gate, diff. C happens in both wires • Use chain of AND plane devices in PLA to determine when to activate OR plane • Not practical in many situations • Use a chain of inverters, instead, for matching • Needs a nominal delay 30% greater than that of matched path Deep Submicron VLSI Des. Lec. 8

18. FO4 Delays vs. Process Deep Submicron VLSI Des. Lec. 8

19. FO4 Delays vs. Supply V Deep Submicron VLSI Des. Lec. 8

20. FO4 Delays vs. T Deep Submicron VLSI Des. Lec. 8

21. FO4 Delays vs. Worst-Case Design Corner Deep Submicron VLSI Des. Lec. 8

22. Summary • Fringing Field Capacitance • Crosstalk • Crosstalk Delay • Crosstalk Noise • Inductance – Important for bond wires to package and signal integrity • Now important for internal chip interconnect Deep Submicron VLSI Des. Lec. 8