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MachXO CPLD Training Module

MachXO CPLD Training Module. What you will learn in this module: MachXO technology MachXO Features & Benefits MachXO Competition Applications & Target Markets How to sell MachXO solutions. SC. 500MHz Fabric 2Gbps I/O with INDEL & AIL circuitry. I/O: 139 - 944. EBR: 1.0 - 7.8Mb.

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MachXO CPLD Training Module

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  1. MachXO CPLD Training Module What you will learn in this module: • MachXO technology • MachXO Features & Benefits • MachXO Competition • Applications & Target Markets • How to sell MachXO solutions

  2. SC 500MHz Fabric 2Gbps I/O with INDEL & AIL circuitry I/O: 139 - 944 EBR: 1.0 - 7.8Mb 90m ECP2M 300MHz Fabric 840Mbps I/O I/O: 144 - 601 EBR: 1.2 - 5.3Mb ECP2 300MHz Fabric 840Mbps I/O EBR: 55 - 1100Kb I/O: 90 - 588 ispCLK XP2 Outputs: 4 - 20 EBR: 166 - 885Kb I/O: 86 - 540 POWR XO LUT: 256-2280, I/O: 78 - 271,EBR: 0 - 27Kb Inputs: 6 - 12 Outputs: 6 - 28 4K/ZE Macrocell: 32-512, I/O: 32 - 212 10k 20k 30k 40k 50k 60k 70k 80k 90k 100k 110k Lattice Product Matrix SRAM FPGAs Mixed Signal Devices 90m 130m “Instant On” Devices Density (LUTs)

  3. MachXO Technology MachXO is a Crossover PLD: Combines features of CPLDs & FPGAs CPLD Features • “Instant-on” • Non-volatile • High pin/logic ratio • Pin-to-pin speed 3.5ns FPGA Features • SRAM-based • Optimized LUT fabric • Integrated PLLs • Embedded Memory Blocks • Internal Oscillator • 130nm FLASH process from Fujitsu • 256 to 2280 LUTs • 78 to 271 I/Os So what’s a LUT ?

  4. A B C D Y A B C D Y A Y B C D MachXO Technology – LUT Look Up Table (LUT) – the Swiss army knife of combinational logic • MachXO uses a 4-input Look Up Table (LUT) • Can create any 4-input combinatorial function • 256 to 2280 LUTs in the XO family • LUT is automatically ‘mapped’ based on behavioral description or schematic instance 4-Input LUT A B C D Y

  5. MachXO Technology – LUT & FF • Register added for each LUT • Register can be a Flip Flop or Latch • Register can be by-passed for combinatorial only functions 4-Input LUT & FF

  6. MachXO Technology – Slice • Slice consists of 2 LUT/Flip Flop pairs • Slice has common CLK, CE, SET & RST for both FFs • Multiple LUTs combined for larger functions • Carry chain for fast arithmetic functions Slice Carry In

  7. MachXO Technology – PFU Programmable Function Unit (PFU) • 4 Slices make up a Programmable Function Unit (PFU) • Similar to Altera MAXII LAB (10 LUT4’s + FF pairs) • Fast arithmetic carry logic for entire LUT chain • Multiple LUTs combined for larger functions • Some PFUs can be implemented as distributed memory Carry In

  8. 16x8 ROM AD[3:0] DO[7:0] WCK 16x8 Single Port RAM 16x4 Pseudo-Dual Port RAM AD[3:0] DO[7:0] RAD[3:0] RDO[3:0] WDO[3:0] WAD[3:0] DI[7:0] DI[3:0] WCK WCK WRE WRE MachXO Technology – Distributed Memory 1 PFU can be configured as the following distributed memory: 128 bits/PFU • Memory sizes can be expanded with extra PFUs • ROMs can be implemented in any PFU • RAMs can be implemented in some of the PFUs • Typical performance 250 to 400 MHz

  9. MachXO 256 MachXO 256 MachXO Technology – Distributed RAM Distributed Memory Increases Efficiency of Buffer/Scratch Pad Implementation Up to 16X Implementation of 128-bit Buffer No distributed memory Distributed memory • Popular as FIFOs to implement clock domain transfers • Use EBR for large memories (more efficient) PFUs Used PFUs Available

  10. FIFO (includes control logic) DI[35:0] CLKB RSTA WE CEW DO[35:0] CLKR RSTB RE RCE FF AF EF AE EBR AD[12:0] DI[35:0] CLK RST WE sysMEM Configuration Options CS[2:0] RAM (Single Port) RAM (Dual Port) ROM RAM (Pseudo Dual Port) ADB[12:0] DIB[17:0] CLKB RSTB WEB CSB[2:0] DOB[17:0] DO[35:0] AD[12:0] DIA[17:0] 8192x1 1024x4 4096x2 512x18 2048x4 256x36* *Not available for dual port RAD[12:0] RD[35:0] RCE RCLK WAD[12:0] EBR EBR CLKA AD[12:0] DO[35:0] RSTA WD[35:0] CLK EBR EBR WEA WCLK CSA[2:0] CE WCE DOA[17:0] WE RST MachXO Technology – sysMEM EBR sysMEM Embedded Block RAM (EBR) • Provides 9k bit blocks (1 in 1220, 3 in 2280) • 275MHz Operation • Efficient Implementation of Memory Buffers • Use EBRs for large blocks of memory

  11. TS TSALL Output data Output data TO DO PAD Fast output data signal Absolute Input data signal Ratioed to VCC Programmable Differential delay element MachXO Technology – sysIO Buffers sysIO Capabilities Up to 8 I/O Banks per device • Ultra high speed 600MHz • Programmable Slew Rate • Programmable Drive Strength • 4-14mA (3.3v, 2.5v, 1.8v) • 4-8mA (1.5v) • 2-6mA (1.2v) • Programmable Pull-up/down, Open Drain • Hotsocketing • Input leakage < 1mA during power-up/down • Power supplies sequenced in any order Supported I/O Standards • LVCMOS (3.3v, 2.5v, 1.8v, 1.5v, 1.2v) • LVTTL • PCI including Clamp Diode • Differential: LVDS, LVPECL, RSDS, BLVDS

  12. MachXO Technology – sysCLOCK PLL sysCLOCK PLL Capabilities • Up to 2 PLLs per device • Frequency: 25 - 420 MHz • Low Output Period Jitter: +/- 125ps • Dynamic Delay Adjust • 2ns lead or lag (250ps steps) • Programmable Phase/Duty Cycle (45o Steps)

  13. MachXO Technology – Routing • Routing resources are used to connect PFUs, EBRs, I/Os & PLLs • Consists of switching circuitry, buffers & metal interconnect segments • Routing segments span 2, 3 & 7 PFUs vertically & horizontally for fast connections • Extensive clock distribution network allows flexibility & minimum skew • ispLever automatically places & routes the design based on synthesis tool output • Interactive routing editor available to optimize the design

  14. OSCC OSCLK Oscillator Primitive COMPONENT OSCC PORT (OSC:OUT std_logic); END COMPONENT; begin OSCInst0: OSCC PORT MAP ( OSC => osc_int ); VHDL instance On-Chip Oscillator • On-Chip Oscillator Provides Low Cost Clock • Ideal for non-timing-critical state machines • Nominal 20Mhz Frequency • Tolerance 17 to 24MHz • Drives Internal Routing • Can be routed off chip • Powered Off When Not In Use • Easily Implemented With ispLEVER Design Tools

  15. 10110010111001010111110001011000 MachXO Technology – FLASH Optimal Programming Sequence Configuration bitstream enters device thru JTAG port Bitstream routed to FLASH block (enables “instant on”) <2sec FLASH configures logic, interconnect and EBRs in SRAM <1ms On-chip FLASH provides Secure single chip solution Massively parallel wide data transfer provides snoop-proof configuration JTAG can load bitstream directly to SRAM <100ms Configuration bitstream generated by ispLever Infinitely reconfigurable SRAM

  16. ROM at t0 ROM at t1 ROM at t2 ROM at t3 EBR EBR EBR EBR 10111001 00011100 01011000 11001011 10111001 00011100 01011000 11001011 11111111 00000000 00000000 11111111 New data Loaded In ROM New data Loaded in ROM 10111001 00011100 01011000 11001011 10111001 00011100 01011000 11001011 11111111 00000000 00000000 11111111 11111111 00000000 00000000 11111111 New data via JTAG Programming in background Initial data via JTAG programming MachXO Technology – FLASH • Each sysMEM EBR is Shadowed by Flash Memory • Allows each bit to be uniquely initialized • Reprogramming FLASH Allows ROM contents to be changed – user PROM

  17. MachXO Technology - Reconfiguration Transparent Field Reconfiguration (TransFR) Enables in-system field updates while the system operates! Reconfiguration Sequence • Power-up with configuration #1 • Background FLASH programming bitstream #2 while logic functions • I/O States are locked in user-defined values • FLASH transfers bitstream #2 to SRAM • Inputs operational, logic initialized, output control reverts to user logic

  18. MachXO Technology – Supply Voltages • “C” Version Provides Access to Latest Technology Without Adding New Power Supplies to Board • Improved performance and power consumption • Supports single supply operation from 3.3v • Operates internally at 1.2v • “E” Version Minimizes Power Consumption • 64% lower power than operation at 3.3v • Operates internally at 1.2v Supply voltages for MachXO devices can be powered up in any sequence

  19. MachXO Technology – Sleep Mode MachXO consumes 100X less static power in Sleep Mode SLEEPN Pin MachXO Device State Normal Sleep Mode Normal <100nS <1mS Sleep Mode is only available on 1.8/2.5/3.3V “C” version devices

  20. tPD = 3.5ns LUT4 D Q V tCO = 4.0ns CLOCK MachXO Technology – Performance Performance supports designs > 250MHz

  21. RoHS TQFP MachXO Family Members Note: only the XO1200 & XO2280 contain EBRs and PLLs. * * Distributed RAM bits are part of the total LUT allocation. csBGA ftBGA

  22. MachXO – Part Numbers

  23. MachXO Features & Benefits

  24. MachXO Features – SRAM + FLASH +TransFR The MachXO SRAM and FLASH architecture coupled with TransFR technology gives you a great opportunity with customers Customer Benefits • In-field logic updates • ASIC/Bug fixes • Standards changes • Equipment upgrades • Additional features • Device upgrade while system is running • “5 Nines”: 99.999% system uptime standard • That’s only 5.3 minutes of downtime per year! • Other vendors do not support this • Fewer components required

  25. MachXO Competition – Altera MAX II

  26. MachXO Competition - Actel ProASIC 3 * Assumes 2.5 Tiles = 1 LUT ** Lowest density device only *** Above 2.5K LUTs

  27. MachXO Apps & Target Markets MachXO General Applications • Bus Interface • Bus Bridging • Data Conversion • Chip Select • Power & Reset Control • ASIC & FPGA Configuration • Memory Control • Signal Distribution • System Power Management • Small ASIC/ASSP Replacement • ASIC Bug Fixes MachXO Target Markets • Industrial: high temp range, high pin/logic ratio • Hand-held Computing: ultra low power sleep mode • Military: security, instant-on • Automotive: high temp range great for cabin apps • Consumer: multiple device integration, small footprint, low cost Here’s where we really shine!

  28. MachXO Apps - Server Clock Domain 33 MHz (F1) 133 MHz Bus 10/100 Ethernet CPU 5512MV MachXO North Bridge Ultra SCSI SDRAM 33 MHz Clock 802.11 Controller South Bridge 5512MV 33 MHz PCI Bus 133 MHz (F2) Multiple Clock Domains Make MachXO with EBR/PLLs Ideal

  29. MachXO Apps - Server Clock Domain (PLL) CLK 1 Out To CPU and Bridges PLL0 VCO Freq = 330 MHz F1 (33 MHZ) CLK IN (33 MHZ) M = 2 V = 10 PGM DLY VCO PLL_Lock K N = 0 Sec_Out PLL_FBK CLK 2 Out To Peripheral Devices PLL1 VCO Freq = 665 MHz F2 (133 MHZ) M = 8 V = 5 PGM DLY VCO PLL_Lock K N = 0 Sec_Out PLL_FBK 16-Bit Reg MachXO Solution • Utilize 2 PLLs • FIFO’s for Data Buffering • EBRs • Minimum Skew CPU Bus Peripheral Bus 16-Bit Reg

  30. MachXO Apps - Base Station Solution Rx/Tx • XO2280 • Leave Alone I/O • 1400 LUTs • 130 LVTTL I/O • Instant-On • 3 EBRs & 1 PLL MPU (RISC or CISC) System Glue Logic Multi-Carrier Power Amplifier Rx SRAM Control Logic MCPA Power Supply Flash Memory LNA DC-DC power supply System Controller Unit RF Tx RF Rx Circuit Switch Control & Signaling Symbol Decode & Demodulation Symbol Encode & Modulation EI/TI PHY Interface Circuitry BSC Interface DAC ADC Network Interface Unit ADC Filtering Broadband Interface Logic Filtering Baseband Unit

  31. MachXO Apps - Node B Remote Radio Head Terminal Bus Ethernet MAC Terminal Terminal Control High Speed Block Utopia, BSII & I2C Power Quicc II • XO2280 • 2200 LUTS • 160 I/O • 2 PLLs • 3 EBRs Clock Distribution FPGA Loader MPC 60x SRAM FLASH

  32. Entertainment • Digital Radio • Radio / HD Radio / DAB • Surround Sound • Telematics • CD/MP3 Player • DVD Player • GPS • Internet Access Body Electronics • Protocol Gateway • Accelerator and Brake Petal Adjustments • Air Bags • Biometrics • Memory Seats • Mirrors • Trip Computer • Windows Advanced Safety Systems • Active Steering • Adaptive Cruise Control • Lane Keeping Assist • Navigation-linked cruise Control • Park/Reverse Assist • Side View Camera • Telematics • Adaptive Headlights • Driver Monitoring • Night View Heads-up display • x-by-wire • Virtual Networks Under-The-Hood • ABS Brakes • Electronic Throttle • Fuel Cell Controller • Hybrid Battery Controller • Powertrain • Regenerative Braking • Transmission MachXO Apps - Automotive Lattice Designed Into Product Opportunity for Lattice Devices MachXO is TS-16949 Certified!

  33. MachXO Apps – Lane Departure System I2C Control 2 MachXO CMOS Imager MT9V125640 x 480 ITU_R BT.656 Microcontroller 8 Sync Valid 3 ITU_R BT.656 *Serializer10b/12b 8 27Mhz Clock Osc * It may be possible to use the MachXO directly drive the 10b/12b output stream RAMFrame Buffer • MachXO Functions: • Receive data from the camera • Store in RAM frame buffer • Perform camera lens distortion correction • Under mcu control, do video overlay functions • Combine video stream from camera with the overlay • Transmission video stream to main controller IP for camera lens fisheye correction: Straighten out the geometries for the bumper and lane information

  34. MachXO - How to Sell • For customers who need a small FPGA • XO has SRAM-based LUT architecture, PLLs, distributed memory & EBRs • For customers who need a CPLD • XO is non-volatile • XO has fast timing (3.5ns pin to pin) • XO is sized to the largest industry CPLD • Know our advantages Over MAXII • Transparent field reconfigurable (TransFR) • Sleep mode provides <100uA static Icc • Integrated PLLs & EBR • If customer insists on a CPLD don’t “unsell” him • CPLD has higher ASPs • Mach 4000 family has long production life cycle • Don’t cannibalize existing Lattice sockets • Sell up • Highlight MachXO’s added capabilities/features that can help his design • Suggest integrating more board functions & migrate to Lattice XP family MachXO is a Crossover PLD

  35. MachXO – Review Questions • Is MachXO a CPLD or an FPGA? • What is the fastest pin to pin delay with MachXO? • How many LUTs are in a MachXO Slice? PFU? • What 3 capabilities does Flash enable on the MachXO devices? • Name 3 I/O standards supported by MachXO. • When should you use EBR instead of distributed RAM? Why? • What is standby current in sleep mode for MachXO devices? • What MachXO devices contain PLLs? EBRs? • What design system speed does MachXO support? • Name 3 applications well suite to MachXO. Do you know the answers to the following review questions?

  36. MachXO - Summary Top 3 things to remember about MachXO: • MachXO has the fast performance of a CPLD (3.5ns pin to pin) • MachXO has the flexibility & high end functions of an FPGA (PLL, EBR) • MachXO has superior value & features compared to Altera MaxII Next Steps: • Review the MachXO Product Brochure (eLearn “Sparkle Sheets” section) • Print the MachXO Part # Guide, page 22. • Review the customer presentation (eLearn “Customer Presentation” section) • Take the MachXO Quiz

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