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Advances in Digital EMC Project: di/dt Measurement Setups and Comparison Analysis

This report presents the latest updates from the Digital EMC project, focusing on di/dt measurement setups (Setup-1, Setup-2, Setup-3) and the comparison of gate counts within inverter chains. Emphasis is placed on both time and frequency domain comparisons, examining issues of peak value timing and waveform harmonics. Various configurations illustrate methods for reducing di/dt, with a discussion on the effective use of decoupling capacitors. The findings highlight the efficacy of MSFF chains in achieving significant di/dt reductions under specific conditions, paving the way for further investigation into digital design insights.

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Advances in Digital EMC Project: di/dt Measurement Setups and Comparison Analysis

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  1. Update of the “Digital EMC project” June 5th, 2007 Junfeng Zhou Promotor: Prof. Wim Dehaene KULeuven ESAT-MICAS

  2. EME and di/dt measurement Setups Setup-3 Setup-2 Setup-1 VCCC =12 V VCC = 4.5 V ~ 8 V VDD2 = 3.3 V i2 i3 i1 EMI-Suppressing Regulator (MICAS) VDD<1..10> Low Drop-out / Serial Regulator AMIS digital load VCC i5 and V2 GND i4 and V1 configuration bits Semi-automatic setup is ready both for time and frequency domain ! PC

  3. Description of the gate counts comparison 1 inverter-chain FFs are connected through MUX Chain 1 MUX MUX Out FF FF FF FF Din CLK RST 60 FF Other 2 inverter chains 9 inverters Chain 2 Chain 3 Chain 4 Chain 5 There are 7 work modes

  4. Some words on the comparison itself • Focus on comparisons in Time Domain: • | di/dt | maximum value • Difficulty in comparison and interpretation in Frequency Domain: • Fundamental or harmonic frequency ? • Is it fair to only compare the PEAK in spectrum ? • How about when peak value happens in different harmonics for different waveform ?

  5. An example Gate counts : condition 4 Gate counts : condition 2 9.87x106 A/s 1.25x107 A/s 60.1 dB uV 56.7 dB uV

  6. Setup-1 – di/dt vs. Slave Clock Domain ( MSFF ) Note: 1. MSFF-chain 1 (no decoupling capacitor ), 2. MSFF - master slave non-overlap time 5.8 ns, 3.Periodic data input, 4. Clk=10 MHz, 1 slave clock domain untitled 1 slave clock domain : Disable delays between slave clock signals SCLK1, SCLK2 and SCLK3. 3 slave clock domains: Enable delays between slave clock signals SCLK1, SCLK2 and SCLK3. 3 slave clock domains Conclusion: Very effective method, more than 2.5 time di/dt reduction,.

  7. Setup-1 – di/dt vs. distributed clock ( MSFF ) Note: 1. MSFF-chain 1 (no decoupling capacitor ), 2. Periodic data input, 3. Clk=10 MHz, master 5.8ns untitled 17.4ns 33ns slave Non-overlap time Discussion: 1. Reduction is quite limited, expected more di/dt reduction ?! 2. Probably more apparent when more chains are on,

  8. Setup-1 – di/dt peak vs. Gate counts Note: 1. Periodic data input, 2. Clk= 10 MHz, 3. MSFF - master slave non-overlap time 5.8 ns. di/dt vs. Gate counts Description of gate counts: 1.Chain 1, neighbouring FFs are connected directly, 2. Chain 1, neighbouring FFs are connected via an inverter chain, + the upper inverter chain toggling, 3. ‘2’ condition + bottom inverter chains toggling, 4. chain 1 and 2 in ‘3’ condition, 5. chain 1, 2 and 3 in ‘3’ condition 6. chain 1, 2, 3 and 4 in ‘3’ condition 7. chain 1, 2 , 3 , 4 and 5 in ‘3’ condition 3 6 2 4 5 7 1 Gate counts linear relationship from 3 ~ 7

  9. Setup-1 – di/dt peak vs. VDD Note: 1.DFF-chain 1 and MSFF-chain 1 (no decoupling capacitor ), 2. MSFF - master slave non-overlap time 5.8 ns 3. Clk = 10MHz, 4. Periodic data input, 5. VDD=1.5v, 2.0v, 2.7v, 3.3v . In First order: di/dt is proportional to VDD

  10. Setup-1 – di/dt vs. Clock Frequency Note: 1.DFF-chain 1 and MSFF-chain 1 (no decoupling capacitor ), 2. MSFF - master slave non-overlap time 5.8 ns 3. Periodic data input, 4. Clk=2.5, 4, 5, 8 ,10 MHz To be discussed the relationship 10 2.5 4 5 8

  11. Setup-1 – di/dt vs. Decoupling Strategy Note: 1. Periodic data input, 2. Clk=8 MHz, 3. MSFF - master slave non-overlap time 5.8 ns 1: No decoupling capacitors. 2: 1/2 times PNMOS decoupling capacitors. 3: PNMOS decoupling capacitors 4: PNMOS decoupling capacitors, with thick metal 4 power ring. 5: MIMC decoupling capacitors next to the chain, with the same capacity value as PNMOS capacitor in the chains 3 and 4. untitled Conclusion: 1. decoupling capa helps to reduce the di/dt, 2. the MIMC capacitor is most effective, 3. Power ring might introduce noise, 1 2 3 4 5 Note: PNMOS means Pseudo-NMOS 1 time PNMOS capacitor = ?? pF

  12. Questions for AMIS and KHBO • What do you really want ? • time domain or frequency domain • Output = Function (Input) ? • If frequency domain ? What is the most important ? • I(w) ? ( spectra of i(t) ) • s*I(w) ? ( spectra of di/dt ) • For which is the Gabarit made ?

  13. Example of spectrum of di/dt 60.1 dB uV Gate counts : condition 4 Gate counts : condition 2 56.7 dB uV 227.7 dB 226.4 dB jw jw

  14. Other conclusion • It seems that MSFF is more di/dt friendly given the same other conditions, • MSFF offers more degrees of freedom for di/dt reduction: • Clock domains, • Distributed Clock  more exploration needed !

  15. Future Work • Interpretation of the measured results, • Time domain, • Frequency domain • Model Construction

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