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Customisable FPGA Platform for Accelerating Floating Point Computations

Customisable FPGA Platform for Accelerating Floating Point Computations. Transfer examination Chun Hok Ho cho@doc.ic.ac.uk. 2 February 2007. Motivations. Floating Point Applications are important Molecular dynamics Physics problems Differential equations Linear systems

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Customisable FPGA Platform for Accelerating Floating Point Computations

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  1. Customisable FPGA Platform for Accelerating Floating PointComputations Transfer examination Chun Hok Ho cho@doc.ic.ac.uk 2 February 2007

  2. Motivations • Floating Point Applications are important • Molecular dynamics • Physics problems • Differential equations • Linear systems • Graphics transformation • Financial engineering

  3. Motivations • Current computing platform for floating point application • Processor-based platform • General purpose • Restricted to von Neumann architecture • Not dedicate to floating point computations • FPGA-based platform • An approach to accelerate computations • Speedup: 10x ~ 1000x against general purpose processor • Not dedicate to floating point computations

  4. Objectives • Methodology for inventing new FPGA architecture • Customisable • Design exploration • Novel customisableFPGA architecture • Efficient floating point computation • Similar programmability as the current FPGA • Associated tools for supporting the architecture, model and methodology

  5. Related work (architecture) • Fine-grained FPGA (Virtex, Stratix) • Embedded blocks (multiplier, DSP) • Fixed point computations • Coarse-grained FPGA • ADRES • RaPiD • Datapath FPGA

  6. Related work (modelling) • Versatile Place and Route (VPR) • place and route on virtual FPGA • flexible architectural parameters • XC4000X device • some version includes carry chain, embedded multiplier, block memory

  7. Related work (applications) • Financial engineering – interest rate derivatives • Image processing – K-means clustering • Physics simulation – N-body problem • Signal processing – Fast Hartley Transform (FHT) • Video processing – noise reducer

  8. Methodology • How to model an FPGA architecture? • What fine-grained architecture? • What coarse-grained architecture? • How to evaluate an FPGA architecture?

  9. Methodology • Modelling • Commercial place and route tool • Synthesisable FPGA fabric model • Exploration • Fine-grained / coarse-grained • Embedding various floating point cores • Evaluation • Benchmark circuits • Compare to existing commercial device

  10. Benchmark circuits • Floating point unit • single/double precision, fully pipelined, subnormal number • Adder and multiplier • implement on ASIC and FPGA • Floating Point benchmark circuits • butterfly (bfly), digital sine-cosine generator (dscg), FIR (fir4), ordinary differential equation solver (ode), 3 x 3 matrix multiplier (mm3), Monte Carlo simulation (bgm)

  11. Modelling • Virtual embedded block design flow • Current vendor’s place and route tools to explore the system performance of embedding various ASIC design, e.g. (block multiplier / FPU) • Synthesisable Datapath FPGA design flow • Fabric generator to develop both generalised and domain specific customisable datapath oriented FPGAs

  12. Virtual embedded blocks (VEB) • Using logic cells to emulate embedded elements in FPGA • Area area of logic cells • Delay combinatorial delays of logic cells • Position placement constraints • Integrate into most of the development tools (commercial or academia) • Requires timing analysis tool and floorplanner • Retiming

  13. Virtual embedded blocks (VEB) • Rapid exploration of embedded elements on existing FPGA • Simple interface, complicated model • Compare commercial FPGA directly • Allow high quality synthesis and optimisation

  14. VEB design flows

  15. Synthesisable fabric • Fabric described in RTL hardware description language • Synthesisable standard ASIC tools (Synopsys Designer Compiler) • Parameterised fabric • Rapid evaluation

  16. Synthesisable fabric • Product-term fine-grained synthesisable core

  17. Hybrid FPGA • VEB model • Arbitrary embedded elements • Vendor specific fine-grained fabric • Dedicated to fine-grained architecture • Synthesisable model • Parameterised coarse-grained fabric • Dedicated to coarse-grained architecture • Combined both?

  18. Hybrid FPGA • Most digital circuits • Control logic  irregular, bit-based logic • Datapath  regular, bus-based logic • Hybrid FPGA • Fine-grained resources  control logic • Coarse-grained resources  datapath

  19. Hybrid FPGA architecture

  20. Coarse-grained fabric

  21. Example floorplan

  22. Future plan • 6 month internship at Xilinx Inc., starting next week • Aug 2007 – Nov 2007: develop high level synthesis algorithm • Dec 2007 – Mar 2008: implement more complex floating point applications • Apr 2008 – Jun 2008: develop automatic hybrid FPGA architecture generation algorithm • Jul 2008 – Nov 2008: thesis writeup

  23. Conclusions • Research direction • Floating Point FPGA • Research methodology • Modelling • Architecture • Future • Automatic FPGA generation

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