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FPGA Encryption/Decryption Verification System Final Presentation

FPGA Encryption/Decryption Verification System Final Presentation. Written by: Yaakov Levenzon Ido Kahan Advisor : Mr. Mony Orbach. Spring Semester 2012. The Problem. We carry sensitive information with us, to practically everywhere…. Where is it?!. Project Goals.

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FPGA Encryption/Decryption Verification System Final Presentation

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  1. FPGA Encryption/Decryption Verification SystemFinal Presentation Written by: Yaakov Levenzon Ido Kahan Advisor: Mr. Mony Orbach Spring Semester 2012

  2. The Problem We carry sensitive information with us, to practically everywhere… Where is it?!

  3. Project Goals • Primary Goal: • The system will serve as a testing system for a given AES,So the system not be depended on the AES module (given it complies to our system’s data sheet). • Secondary Goals: • Understanding and developing ways of communication between the PC and the DE2 board and its internal memory, by using DLP-245M. • Understanding and implementing the Nios ІІ embedded processor, and transfer data by utilizing the Avalon bus. • Designing and implementing a simple Encryption/Decryption Module into our system.

  4. Architecture – High Level DE2 FPGA controller Nios II Host PC DLP AVALON USB Encryption /Decryption Out_Data FIFO 128->8 In_Data FIFO 8->128

  5. DLP – USB245M

  6. Block Diagram – Writing to FPGA FPGA DLP PC FIFO Sending words Words by USB protocol Words on AVALON bus Unencrypted words PC PC Nios Nios FPGA DLP PC FIFO Encrypt/decrypt Words on AVALON bus Words by USB protocol Saving words Nios Nios PC PC Encrypting words Encrypted words

  7. Block Diagram – Reading from FPGA Exactly the same data-flow FPGA DLP PC FIFO Sending words Words by USB protocol Words on AVALON bus Undeciphered words PC PC Nios Nios FPGA DLP PC FIFO Encrypt/decrypt Words on AVALON bus Words by USB protocol Saving words Nios Nios PC PC decipher words deciphered words

  8. Detailed Architecture Example to an AES - Based on previous project specs: TP: 763 MB/s CLK freq: 57.88 MHz Tot LES: 11,463 (35%)Tot Memory bits: 327,680 (68%) Encryption system NOT gate EncryptionDecryption AES EncryptsDecoder FIFO 128->8 PC CTRL CTRL PC-USB CTRL DLP Read enable from counter (gets AES enable) CTRL Nios Host Instruction Memory 4k bits USB protocol(1 MB/s) DE2 protocol FIFO 8->128 en from counter Valid_data_out 128 bit USB DLP CTRL FULL 8 8 bit 8 128 8 Min 16 words => 1 block cipher Key- 128 128 8 Key string- 128 Nios II/e FULL Register 128 bits One source file divided into small files Data Controller CLK freq: 200 MHz 1738 LES (5%) Total mem bits 43264 (9%) 16 bits data bus 1 MB/s data transfer rate to DLP 245M Uses the Avalon Bus AES enable FIFO read enable Clk (input)

  9. Nios II animation • Nios II/e Core – enough for our needs • Can access up to 2 GB of external address space • Memory requirements (making room for the encryption/decryption system) • The NIOS II “Hello World & counter leds” program worked on this system as well(but with much less memory consumption)

  10. Top Level Nios Encrypt_sys Fifo_out FSM Fifo_in controller

  11. Top Level- Compilation

  12. GUI for the user

  13. Our System’s Data Sheet • Maximum possible Encryption/Decryption memory size: 221696 bits (46%) • (Recommended size – for 85% capacity: 149120 bits) • Maximum possible Encryption/Decryption number of LE: 32645 • Key Size: 128 bits • Data width: 128 bits • System speed: 1 MBPS (dictated by the DLP module) • DLP FIFO size: 1024 bits • DLP FIFO Speed: 384 byte Transmit buffer / 128 byte receive buffer

  14. Bugs and notes • Compilation error while working on Altera and TerAsic example files, using NIOS II IDE

  15. Bugs and notes - Continued • Tri-state didn’t work while using in-out port

  16. Matlab – Picture processing and encrypting

  17. Summary and conclusions • The project goals were fully accomplished. • We understood the importance of Encryption/Decryption systems, and their complexity. • We now appreciate the value of a great quality Verification system.It is that small factor which makes the difference between very good products and excellent products in the market. • Architecture design is hard, but a very interesting field. • We enjoyed the project very much, and would like to thank our advisor, Mr. Mony Orbach.

  18. Planning ahead • Implementing AES into our system. • Working with SD-Card & Flash Memory. • Speed Improvements • Better Interface for the novice user.

  19. Thank you for listening

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