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SEQ CPU Implementation

SEQ CPU Implementation. Outline. SEQ Implementation Suggested Reading 4.3.1, 4.3.4. Fetch. icode:ifun  M 1 [PC]. Read instruction byte. rA:rB  M 1 [PC+1]. Read register byte. valP  PC+2. Compute next PC. Decode. valA  R[rA]. Read operand A. valB  R[rB]. Read operand B.

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SEQ CPU Implementation

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  1. SEQ CPU Implementation

  2. Outline • SEQ Implementation • Suggested Reading 4.3.1, 4.3.4

  3. Fetch icode:ifun  M1[PC] Read instruction byte rA:rB  M1[PC+1] Read register byte valP  PC+2 Compute next PC Decode valA  R[rA] Read operand A valB  R[rB] Read operand B Memory Write back R[rB]  valE Write back result PC update PC  valP Update PC Stage Computation: opl OPl rA, rB Execute valE  valB ifun valA Perform ALU operation Set CC Set condition code register

  4. Data memory ALU PC increment PC Write back valM Memory addrs,data valE CC Cnd CC CC Execute valA,valB valA, valB rA, rB Decode A B Register File M E M Register rB,dstM icode:ifun, rA:rB valC valE, valM valP Instruction memory Instruction Fetch PC PC PC valP

  5. Fetch icode:ifun  M1[PC] Read instruction byte rrmovl rA, rB rA:rB  M1[PC+1] Read register byte valP  PC+2 Compute next PC Decode valA  R[rA] Read operand A Execute valE  0 + valA Perform ALU operation (generalization) Memory Write back R[rB]  valE Write back result PC update PC  valP Update PC Stage Computation: rrmovl

  6. Data memory ALU PC increment PC Write back valM Memory addrs,data valE CC Cnd CC CC Execute valA,0 valA, valB rA, srcB Decode A B Register File M E M Register rB,dstM icode:ifun, rA:rB valC valE, valM valP Instruction memory Instruction Fetch PC PC PC valP

  7. irmovl rA, rB Fetch icode:ifun  M1[PC] Read instruction byte rA:rB  M1[PC+1] Read register byte valC  M4[PC+2] Read constant value valP  PC+6 Compute next PC Decode Execute valE  0 + valC Perform ALU operation (generalization) Memory Write back R[rB]  valE Write back result PC update PC  valP Update PC Stage Computation: irmovl

  8. Data memory ALU PC increment PC Write back valM Memory addrs,data valE CC Cnd CC CC Execute valC,0 valA, valB srcA, srcB Decode A B Register File M E M Register rB,dstM icode:ifun, rA:rB valC valE, valM valP Instruction memory Instruction Fetch PC PC PC valP

  9. Fetch Read 6 bytes Decode Read operand registers Execute Compute effective address Memory Write to memory Write back Do nothing PC Update Increment PC by 6 rA rB 4 0 rmmovl rA, D(rB) D Executing rmmovl

  10. rmmovl rA, D(rB) Fetch icode:ifun  M1[PC] Read instruction byte rA:rB  M1[PC+1] Read register byte valC  M4[PC+2] Read displacement D valP  PC+6 Compute next PC Decode valA  R[rA] Read operand A valB  R[rB] Read operand B Execute valE  valB + valC Compute effective address Memory M4[valE]  valA Write value to memory Write back PC update PC  valP Update PC Stage Computation: rmmovl • Use ALU for address computation

  11. Data memory ALU PC increment PC Write back valM Memory valE,valA valE CC Cnd CC CC Execute valC,valB valA, valB rA, rB Decode A B Register File M E M Register dstE,dstM icode:ifun, rA:rB valC valE, valM valP Instruction memory Instruction Fetch PC PC PC valP

  12. Fetch Read 6 bytes Decode Read operand register rB Execute Compute effective address Memory Read from memory Write back Update register rA PC Update Increment PC by 6 rA rB 5 0 mrmovl D(rB),rA D Executing mrmovl

  13. mrmovl D(rB) , rA Fetch icode:ifun  M1[PC] Read instruction byte rA:rB  M1[PC+1] Read register byte valC  M4[PC+2] Read displacement D valP  PC+6 Compute next PC Decode valB  R[rB] Read operand B Execute valE  valB + valC Compute effective address Memory valM  M4[valE] Read data from memory Write back R[rA]  valM Update register rA PC update PC  valP Update PC Stage Computation: mrmovl • Use ALU for address computation

  14. Data memory ALU PC increment PC Write back valM Memory valE,data valE CC Cnd CC CC Execute valC,valB valA, valB srcA, rB Decode A B Register File M E M Register dstE,rA icode:ifun, rA:rB valC valE, valM valP Instruction memory Instruction Fetch PC PC PC valP

  15. Fetch Read 2 bytes Decode Read stack pointer and register rA Execute Decrement stack pointer by 4 Memory Store valA at the address of new stack pointer Write back Update stack pointer PC Update Increment PC by 2 pushl rA a rA 0 F Executing pushl

  16. pushl rA Fetch icode:ifun  M1[PC] Read instruction byte rA:rB  M1[PC+1] Read register byte valP  PC+2 Compute next PC Decode valA  R[rA] Read valA valB  R [%esp] Read stack pointer Execute valE  valB + (-4) Decrement stack pointer Memory M4[valE]  valA Store to stack Write back R[%esp]  valE Update stack pointer PC update PC  valP Update PC Stage Computation: pushl • Use ALU to decrement stack pointer

  17. Data memory ALU PC increment PC Write back valM Memory valE,valA valE CC Cnd CC CC Execute -4,valB valA, valB rA, %esp Decode A B Register File M E M Register %esp,dstM icode:ifun, rA:rB valC valE, valM valP Instruction memory Instruction Fetch PC valP

  18. Fetch Read 2 bytes Decode Read stack pointer Execute Increment stack pointer by 4 Memory Read from old stack pointer Write back Update stack pointer Update register rA PC Update Increment PC by 2 popl rA b rA 0 F Executing popl

  19. popl rA Fetch icode:ifun  M1[PC] Read instruction byte rA:rB  M1[PC+1] Read register byte valP  PC+2 Compute next PC Decode valA  R[%esp] Read stack pointer valB  R [%esp] Read stack pointer Execute valE  valB + 4 Increment stack pointer Memory valM  M4[valA] Read from stack Write back R[%esp]  valE Update stack pointer R[rA]  valM Write back result PC update PC  valP Update PC Stage Computation: popl update two registers (special: rA=%esp) • Use ALU to increment stack pointer

  20. Data memory ALU PC increment PC Write back valM Memory valA,data valE CC Cnd CC CC Execute +4,valB valA, valB %esp, %esp Decode A B Register File M E M Register %esp,rA icode:ifun, rA:rB valC valE, valM valP Instruction memory Instruction Fetch PC PC PC valP

  21. jXX Dest Dest Not taken fall thru: target: Taken 7 XX XX fn XX XX Executing Jumps

  22. Fetch Read 5 bytes Increment PC by 5 Decode Do nothing Execute Determine whether to take branch based on jump condition and condition codes Memory Do nothing Write back Do nothing PC Update Set PC to Dest if branch taken or to incremented PC if not branch Executing Jumps

  23. Fetch icode:ifun  M1[PC] Read instruction byte valC  M4[PC+1] Read destination address valP  PC+5 Fall through address Decode Memory Write back PC update PC  Cnd ? valC : valP Update PC Stage Computation: Jumps jXX Dest Compute both addresses Execute Cnd  Cond(CC,ifun) Take branch? Chose based on CC and ifun

  24. Data memory ALU PC increment PC Write back valM Memory addrs,data valE CC Cnd CC CC Execute aluA,aluB valA, valB srcA, srcB Decode A B Register File M E M Register dstE,dstM icode:ifun, rA:rB valC valE, valM valP Instruction memory Instruction Fetch PC PC PC valP, valC

  25. call Dest Dest return: target: XX XX 8 XX 0 XX Executing call

  26. Fetch Read 5 bytes Increment PC by 5 Decode Read stack pointer Execute Decrement stack pointer by 4 Memory Write incremented PC to new value of stack pointer Write back Update stack pointer PC Update Set PC to Dest Executing call

  27. call Dest Fetch icode:ifun  M1[PC] Read instruction byte valC  M4[PC+1] Read destination address valP  PC+5 Compute return point Decode valB  R[%esp] Read stack pointer Execute valE  valB + –4 Decrement stack pointer Memory M4[valE]  valP Write return value on stack Write back R[%esp]  valE Update stack pointer PC update PC  valC Set PC to destination Stage Computation: call Store incremental PC • Use ALU to decrement stack pointer

  28. Data memory ALU PC increment PC Write back valM Memory valE, valP valE CC Cnd CC CC Execute -4,valB valA, valB srcA, %esp Decode A B Register File M E M Register %esp,dstM icode:ifun, rA:rB valC valE, valM valP Instruction memory Instruction Fetch PC PC PC valC

  29. ret return: XX XX 9 0 Executing ret

  30. Fetch Read 1 byte Decode Read stack pointer Execute Increment stack pointer by 4 Memory Read return address from old stack pointer Write back Update stack pointer PC Update Set PC to return address Executing ret

  31. ret Fetch icode:ifun  M1[PC] Read instruction byte Decode valA  R[%esp] Read operand stack pointer valB  R[%esp] Read operand stack pointer Execute valE  valB + 4 Increment stack pointer Memory valM  M4[valA] Read return address Write back R[%esp]  valE Update stack pointer PC update PC  valM Set PC to return address Stage Computation: ret • Use ALU to increment stack pointer

  32. Data memory ALU PC increment PC Write back valM Memory valA,data valE CC Cnd CC CC Execute 4,valB valA, valB %esp,%esp Decode A B Register File M E M Register %esp, dstM icode:ifun, rA:rB valC valE, valM valP Instruction memory Instruction Fetch PC PC PC valM

  33. Fetch Read 2 bytes Decode Read operand register rA Execute Determine whether to move Memory Do nothing Write back Update register rB if move taken PC Update Increment PC by 2 cmovXX rA, rB 2 fn rA rB Executing cmovXX

  34. Fetch icode:ifun  M1[PC] Read instruction byte rA:rB  M1[PC+1] Read register byte valP  PC+2 Compute next PC Decode valA  R[rA] Read operand A Memory PC update PC  valP Update PC Stage Computation: cmovXX cmovXX rA, rB Execute valE  0 + valA Perform ALU operation Cnd  Cond(CC,ifun) Take move? Write back Cnd ? R[rB]  valE : - Write back result if move taken

  35. Data memory ALU PC increment PC Write back valM Memory addrs,data valE CC Cnd CC CC Execute valA,0 valA, valB rA, srcB Decode A B Register File M E M Register rB,dstM icode:ifun, rA:rB valC valE, valM valP Instruction memory Instruction Fetch PC PC PC valP

  36. Computation Steps OPl rA, rB • All instructions follow same general pattern • Differ in what gets computed on each step Fetch icode,ifun icode:ifun  M1[PC] Read instruction byte rA,rB rA:rB  M1[PC+1] Read register byte valC Read constant word valP valP  PC+2 Compute next PC Decode valA, srcA valA  R[rA] Read operand A valB, srcB valB  R[rB] Read operand B Execute valE valE  valB OP valA Perform ALU operation Cond code Set CC Set condition code reg. Memory valM Read/Write Memory Write Back dstE R[rB]  valE Write back ALU result dstM Write back Memory result PC update PC PC  valP Update PC

  37. Computation Steps OPl rA, rB call Dest • All instructions follow same general pattern • Differ in what gets computed on each step Fetch icode,ifun icode:ifun  M1[PC] icode:ifun  M1[PC] rA,rB rA:rB  M1[PC+1] valC valC  M4[PC+1] valP valP  PC+2 valP  PC+5 Decode valA, srcA valA  R[rA] valB, srcB valB  R[rB] valB  R[%esp] Execute valE valE  valB OP valA valE  valB + –4 Cond code Set CC Memory valM M4[valE]  valP Write Back dstE R[rB]  valE R[%esp]  valE dstM PC update PC PC  valP PC  valC

  38. Data memory ALU PC increment PC Write back valM Memory addrs,data valE CC Cnd CC CC Execute aluA,aluB valA, valB srcA, srcB Decode A B Register File M E M Register dstE,dstM icode:ifun, rA:rB valC valE, valM valP Instruction memory Instruction Fetch PC PC PC newPC

  39. Fetch PC Program Count icode Instr. Code ifun Instr. Function rA Instr. Register A rB Instr. Register B valC Instr. Constant valP Incremented PC Decode valA Register value A valB Register value B Execute valE ALU result CCCondition Code Cnd Condition Flag Memory valM Value from Memory Write back valEALU result valMValue from Memory Determinate Values

  40. Decode srcA location of valA rA, %esp srcB location of valB rB, %esp Execute aluA input A of ALU valA, valC, +4, -4 aluB input B of ALU valB, 0 Memory addr address of memory valA, valE data data of Memory valA, valP Write back dstE dest. of ALU result rB, %esp dstM dest of Memory rA PC newPC next of PC valP, valC, valM Indeterminate Values

  41. Data memory ALU PC increment PC Write back valM Memory addrs,data valE CC Cnd CC CC Execute aluA,aluB valA, valB srcA, srcB Decode A B Register File M E M Register dstE,dstM icode:ifun, rA:rB valC valE, valM valP Instruction memory Instruction Fetch PC PC PC newPC

  42. SEQ Summary • Sequential Processor (SEQ) • Combinational logic + Sequential logic • Instruction executes in sequential • Every Instruction finished in one cycle. • Express every instruction as series of simple steps • Fetch, Decode, Execute, Memory, Write Back, PC

  43. Difference between semantics and implementation • ISA • Every stage may update some states, these updates occur sequentially • SEQ • All the state update operations occur simultaneously at clock rising

  44. SEQ Semantics • Achieve the same effect as a sequential execution of the assignment shown in the tables of Figures 4.18 to 4.21 • Though all of the state updates occur simultaneously at the clock rises to the next cycle. • A problem: popl %esp need to sequentially write two registers. So the register file control logic must process it.

  45. Data memory ALU Data srcA srcB srcA srcB PC increment valP PC PC newPC New PC data out valM read Memory Mem Control write Addr Bch valE Execute ALU fun CC ALUA ALUB valA valB dstE dstM Decode dstE dstM A B M Register file E Write Back icode ifun rA rB valC Instruction Memory Fetch 46

  46. SEQ Hardware • Blue boxes: predesigned hardware blocks • e.g., memories, ALU • Gray boxes: control logic • Describe in HCL • White ovals: labels for signals • Thick lines: 32-bit word values • Thin lines: 4-8 bit values • Dotted lines: 1-bit values

  47. Fetch Logic

  48. Fetch Logic • Predefined Blocks • PC: Register containing PC • Instruction memory: Read 6 bytes (PC to PC+5) • Split: Divide instruction byte into icode and ifun • Align: Get fields for rA, rB, and valC

  49. Fetch Logic • Control Blocks • Instr. Valid: Is this instruction valid? • Need regids: Does this instruction have a register bytes? • Need valC: Does this instruction have a constant word? • icode|ifun: Set to “nop” if imem_error

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