Boundary Scan

1. Boundary Scan Sungho Kang Yonsei University

2. Outiline • Introduction • TAP Controller • Instruction Register • Test Data Registers • Instructions • Hardware Test Innovations • PCB Test • Conclusion

3. Boundary Scan Introduction • Improve testability by reducing the requirements placed on the physical test equipment • Also called • JTAG (Joint Test Action Group) Boundary Scan Standards • IEEE P1149.1 • Why use it? • Testing interconnections among chips • Testing each chip • Snapshot observation of normal system data • Why testing boards? • To test board is easier than to test systems • Board Test Philosophy • As a sorting process • As a repair driver • As a process monitor

4. Boundary Scan Chip Architecture Introduction • The scan paths are connected via the test bus circuitry • Connection from TDI to Sin • Connection from TDO to Sout • The normal I/O terminals of the application logic are connected through boundary scan cells to the chips I/O pads • Operation • An instruction is sent serially over the TDI line into the instruction register • The selected test circuitry is configured to respond to the instruction • The test instruction is executed and then test results can be shifted out of selected registers and transmitted over the TDO to the bus master • Possible to shift new data into registers using the TDI while results are shifted out and transmitted over the TDO line

5. Boundary Scan Chip Architecture Introduction

6. Board Test Introduction • Board containing 4 chips with one serial test path

7. Cost of Boundary Scan Introduction • Costs • 4 or 5 pins - Test Access Port (TAP) • 16 state machine - TAP controller • Boundary scan register • Bypass register - one stage • Instruction register - 2 or more stages • Impacts • Enhanced diagnosis • Reduced test-repair looping • Standardized tests • Reuse of tests • Reduced access problems

8. Boundary Scan Introduction • Subject Indicator • Design Engineering - IC design - • - Reusable test vectors + • - Test pattern generation ++ • - Board design time - • - Board prototyping ++ • Manufacture - Test pattern generation ++ • - Test time ++ • - Material costs - • - Diagnosis ++ • - Repair + • - Retest + • - Test equipment costs ++ • Commisioning - Diagnosis and repair ++ • Field Maintenance - Diagnosis ++ • - Replacement and repair + • Marketing - Time-to-market ++

9. Test Access Port TAP • Consisting of the ports associated with TMS, TCK, TDI and TDO • TCK: Test Clock • Operate BS part of the ICs synchronously and independently of the built-in system clock • TDI : Test Data In • Data is shifted in at the rising edge • TDO: Test Data Out • Data is shifted out at the falling edge • TMS: Test Mode Select • TMS signals are sampled at the rising edge • Controls transitions of controller • TRST : Test Reset (Optional) • TAP's test logic is asynchronously forced into its reset mode when a logic 0 is applied to TRST

10. Test Bus TAP • Each chip is considered to be a bus slave and the bus is assumed to be driven a bus master • Ring Connection • One TMS • Star Connection • Each chip is associated with its own TMS signal • Hybrid Connection • Combined

11. Ring and Star Test Bus TAP

12. Functions of TAP Controller TAP • Generate clock and control signals required for the correct sequence of operations • Provide signals to allow loading the instructions into the Instruction Register • Provide signals to shift test data into (TDI) and test result data out of (TDO) the shift registers • Perform test actions such as capture, shift and test data

13. TAP Controller State Diagram TAP • Non-shaded states : auxiliary • Do not initiate a system action but are included to provide process control

14. TAP Controller State Diagram TAP • Test-Logic-Reset • The test logic is disabled so that the application logic can operate in its normal mode • Run-Test/Idle • Control state that exists between scan operations and where an internal test, such as built-in self test can be executed • Select-DR-Scan • Temporary control state • If TMS is held low then a scan data sequence for the selected test data register is initiated, starting with a transition to the state Capture-DR • Capture-DR • Data can be loaded in parallel into the test data registers selected by the current instruction

15. TAP Controller State Diagram TAP • Shift-DR • Test data registers specified by the data in the instruction register, and which lie between TDI and TDO, are shifted one position • A new data value enters the scan path via TDI and a new data value now is observed at TDO • Other registers hold their state • Exit1-DR • All test data registers selected by the current instruction hold their state • Pause-DR • The test data registers in the scan path between TDI and TDO hold their state • Often necessary during the transmission of long test sequences • Allow synchronization between TCK and system clock signals

16. TAP Controller State Diagram TAP • Exit2-DR • All test data registers selected by the current instruction hold their state • Update-DR • Test data registers specified by the current instructions and having a latched parallel output feature are loaded from their associated shift registers • -IR • Similarly defined • The states that control instruction register operate similarly to those controlling the test-data registers • Instruction register is implemented using a latched parallel output feature

17. Test-Logic-Reset TAP • All test logic is disabled i.e. all system logic operates normally • Whatever the state is, it will enter the Test-Logic-Reset state when the TMS signal is high for at least 5 rising edge of TCK • Controller remains this state while TMS is high • If TRST is present, it can be used to force the controller to the Test-Logic-Reset state at once

18. Run-Test/Idle TAP • Controller state between the various scan operations • Once the controller is in this state, it will stay there as long as the TMS is low • The current instruction does not change while the controller is in this state

19. Capture-DR TAP • Data is parallel-loaded from the parallel inputs into the selected test data register • The register retains its previous state if it does not have a parallel input or if capturing is not required for the selected test • The action takes place at the rising edge of TCK

20. Shift-DR TAP • The previously captured data is shifted out towards the TDO, one shift register stage on each rising edge of TCK

21. Update-DR TAP • The shifting process has been completed • Test data registers may be provided with a latched parallel output • This prevents the parallel output from changing while data is shifted into the associated shift register path • When these test data registers are selected by an instruction, the new data is latched into their parallel outputs in this state at the falling edge of TCK

22. Capture-IR TAP • Previously shifted-in instruction data is parallel-loaded into the shift-register stage of the instruction register • Design specific data may be loaded into a shift register stage which may not be set to a fixed value • The IR-path between TDI and TDO can be checked as to whether or not the instructions can be shifted in correctly or not • Actions takes place at the rising edge of TCK

23. Shift-IR TAP • The previously captured data is shifted out towards the TDO, one shift-register stage on each rising edge of TCK • Selected test data registers retain their previous state

24. Update-IR TAP • The shifted-in instruction data is loaded from the shift register stage into the parallel instruction register • The new instruction becomes valid when the TAP controller is in this state • All the test data shift register stages which are selected by the current instruction retain their previous values • Actions takes place at the falling edge of TCK

25. Instruction Register Instruction Register • Allows instruction to be shifted into chip • Can be used to specify operations to be executed and select test data registers • Each instruction enables a single serial test data register path between TDI and TDO • Instruction may vary per IC on the board • Serial-in parallel-out register

26. Instruction Register Instruction Register • IR must contain at least 2 shift-register-based cells which can hold instruction data • These 2 mandatory cells are located nearest to the serial outputs, i.e. they are the least significant bits • Used in locating faults through the IC's • Set up

27. Instruction Register Instruction Register • IR operations in each TAP controller state • Controller state Shift register stage Parallel output • Test-Logic-Reset Undefined Set to give the IDCODE(or BYPASS) • Capture-IR Load 01 into LSBs and Retain last state design-specific data or fixed values into MSBs • Shift-IR Shift towards serial Retain last state output • Exit1-IR Retain last state Retain last state • Exit2-IR Retain last state Retain last state • Paste-IR Retain last state Retain last state • Update-IR Retain last state Load from shift register stage into decoder • All other states Undefined Retain last state

28. Test Data Registers Test Data Register • Required • Boundary Scan Register • Bypass Register • Optional • Device Identification Register : specifies manufacturer, part number, and variant • Design Specific Register : for self test, internal scan paths, etc. • Unique Name • Fixed Length

29. Test Data Registers Test Data Register

30. Test Data Registers Test Data Register • Operation of the test data register • Controller state Action • Capture-DR Load data at parallel input into shift-register stage Parallel output register or latch retains last state • Shift-DR Shift data towards serial output • Parallel output register or latch retains state • Exit1-DR Retain last state • Exit2-DR Retain last state • Pause-DR Retain last state • Update-DR Load parallel output register or latch from shift register stage Shift register stage retains state • All other Registers which have a parallel output maintain their control states last state of the output Otherwise undefined

31. Bypass Register Bypass Register • Single stage shift register • When selected, the shift register is set to 0 on the rising edge of TCK with • TAP controller in its Capture-DR state • Provide a minimum length serial path for the test data from TDI to TDO • Test cycle is shortened • Diagnosis time is shortened

32. Boundary Scan Register Scan Cell • Series of boundary scan cells • Features • Allow testing of circuitry external to the IC • Allow testing of the core logic • Allow sampling and examination of the input and output signals without interfering the operation of the core logic • Can stay idle

33. Boundary Scan Cells Scan Cell • Allow testing of board interconnections • Control of each output pin • Observation of all pin states • Boundary scan cells at • Input pins • Output pins • Bi-directional pins • Output driver enables • Direction controls

34. Boundary Scan Cells Scan Cell • Implementation of boundary scan cell • Normal Mode • When Mode Test/Normal = 0, data passes from IN to OUT • Then the cell is transparent to the application logic • Scan Mode • Mode Shift/Load =1 and clock pulses are applied to Clock • Capture Mode • The data on IN can be loaded into the scan path by setting Mode Shift/Load =0 and applying one clock pulse to Clock

35. Boundary Scan Cells Scan Cell • Update Mode • Once the 1st FF is loaded, either by a capture or scan operation, its value can be applied to OUT by setting Mode Test/Normal=1 and applying clock pulse to Update • Minimum boundary scan cell configuration for input pins • Preferrable in delay sensitive circuits

36. Cells at 2-State Output Pins Scan Cell • Can be set only at a high or low logic level • One boundary scan cell is sufficient to observe or control the state of the pin • Boundary scan cell should be designed to avoid the following problems • An external block may contain asynchronous logic that will be set into undesirable states when shifting patterns appear at its input • Boundary scan output signals may be fed into a clock input of the external block, which may produce hazardous effects if the logic is not shielded from the shifting patterns

37. Cells at 3-State Output Pins Scan Cell • 2 boundary scan cells per pin are needed to observe and control the state of the pin • Cell configuration at a 3-state output pin

38. Cells at 3-State Output Pins Scan Cell • When 2 or more 3-state pins are present (e.g. connected to a bus) is is allowable to control the respective enable stages with one boundary scan cell • One boundary scan cell controls several 3-state outputs

39. Cells at Bidirectional Pins Scan Cell • Bidirectional pins may be either a 2-state or a 3-state pin • One boundary scan cell controls several 3-state outputs • Control cell may have an extra input for Reset signal

40. Device ID Register Scan Cell • 32 bit shift-register, parallel-in and serial out • Provide binary information about the manufacturer's name, part number and version number of IC • Applications • In the factory, it allows verification that the correct IC has been mounted on the proper place • When IC has been replaced, the version number of the replacement can be checked, and if required the test program can be modified • It may be desirable to blindly interrogate a PCB design by a controller unit in order to determine the type of each component on each board location without further functional knowledge of the design • When a PCB is added to a configuration at system level, the system test program can be adjusted to the new PCB and the ICs mounted on it • The correct programming of off-line programmed ICs can be checked

41. Device ID Register Scan Cell • Structure of a Device ID Register • If optional Device ID register is not present, Bypass register is chosen when IDCODE is executed • If the first bit shifted out of the component during a test data scan is 0 it can be deduced that component has no Device ID register • Device ID Design

42. Design Specific Register Design Specific Register • The manufacturer may add test data registers dedicated to his own design • The manufacturer may decide whether he makes the instructions for the design specific register available in his component catalogue or not • Otherwise he needs the design specific registers only for his own in-house testing

43. Instructions Instructions • Mandatory • BYPASS • SAMPLE/PRELOAD • EXTEST • Optional • INTEST • RUNBIST • IDCODE • USERCODE • CLAMP • HIGHZ • Design specific

44. BYPASS Instructions • Every chip must have a BYPASS register which is a test data register of length 1 • Provides a single bit connection through the chip • data shifted through chip without affecting chip • shorten path to target chip • Binary code must be all 1's • If the optional device ID is not present, BYPASS instruction is forced into the latches at the parallel outputs of the Instruction Register when the TAP controller is in its Test-Logic-Reset

45. SAMPLE/PRELOAD Instructions • Used to take snapshot of normal system operation stage into the parallel instruction register • Allows the data on I/O pads of a chip to be sampled • Useful for debugging of prototypes in the development phase of a board design • Used to load values into boundary Scan cells • After power-up, the data in boundary scan registers at the output cells are not known

46. SAMPLE Instructions • Instruction • In the sampling mode, data are captured with the TAP controller in its Capture-DR state at the rising edges of TCK • Subsequently these data can be shifted out in the Shift-DR state of the controller • Sampled data can be scanned out while the board remains in normal operation • Dataflow

47. PRELOAD Instructions • When the user prepares an EXTEST by shifting in beforehand the data which must be driven out from the chip's output pins into the PCB net using the TAP controller in its Update-DR state • Dataflow during PRELOAD instruction

48. EXTEST Instructions • Used to test circuitry external to a chip, such as the board interconnect • While this instruction is executed, the core logic is isolated from the I/O pins • The test data is loaded beforehand into the boundary scan register stages using SAMPLE/PRELOAD • The loading of test vectors is concluded by bridging the TAP controller to the Update-DR state • On the falling edge of TCK the test vectors are transferred to the parallel output stage • At the receiving ends of the net, the cells at the input pins capture the test result with the controller in its Capture-DR state • The next step shifts out the test results from the input pin cells towards TDO

49. EXTEST Instructions • Dataflow during EXTEST instruction • During the time of execution of the EXTEST, only one system pin is driving a net at a time while the other connected output pins are kept at HIGHZ • This avoids boundary scan cells at the output pins being overdriven with an unknown signal value

50. EXTEST Instructions • Shift-DR • Shift stimulus data in from TDI through the registers to the cells related with the output pins of the IC • Update-DR • Update these output cells and apply stimuli to the board interconnections • Capture-DR • Capture the status of the board's interconnections at the input pins of the receiving IC • Shift-DR • Shift out the results through the BSR towards TDO for examination