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UNLOCKING THE POWER OF BOUNDARY-SCAN

UNLOCKING THE POWER OF BOUNDARY-SCAN. World Wide Users . 3Com ABB August Systems AGFEO Alcatel AscomTelecom. Atlas Copco Barco Graphics Blaupunkt Bofors Celestica Compaq Datex ECI EKB. Ericsson Ericsson Intracom Force Computer Fujitsu Microelectronics Fujitsu Telecom

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UNLOCKING THE POWER OF BOUNDARY-SCAN

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  1. UNLOCKING THE POWER OF BOUNDARY-SCAN

  2. World Wide Users • 3Com • ABB • August • Systems • AGFEO • Alcatel • AscomTelecom. • Atlas Copco • Barco Graphics • Blaupunkt • Bofors • Celestica • Compaq • Datex • ECI • EKB Ericsson Ericsson Intracom Force Computer Fujitsu Microelectronics Fujitsu Telecom GEC Alsthom Harris Hewlett-Packard Hirschmann Hitachi Consumer Hitachi Microsystems Honeywell Regels. Italtel Research Centre Japanese Radio Corp. Kontron MarPoss • Philips • MedicalSystems • Pioneer • Polytechnico di T. • Rolls Royce • Siemens Medical • Siemens Nixdorf • Sogitec • Solectron • Sony • Sun Microsystems • Telefunken • Thomson • Tokyo MITC • Toshiba Matra Matra Communications Matra-Ericsson T. Matsushita MET Mitsubishi Electric Motorola NEC Technologies Nokia Mobile Comm. NORTEL NTT Parsytec Philips BCS Philips CE Philips CFT

  3. Uniform tools across multiple departments Rapid development cycles, shorter time-to-market High-speed production rates Low initial investment and low cost of ownership Comprehensive supporting services Value

  4. IEEE 1149.1 Boundary-Scan Standard • Adopted in 1990 by the IEEE as Standard 1149.1 • Prepared by the Joint Test Action Group (JTAG) • Originally for testing boards and devices • Provides a serial 4-wire (5th is optional) interface, regardless of device complexity • Semi-conductor manufacturer responsible for: • Designing device for compatibility • Providing BSDL file • Many of today’s key components contain Boundary-Scan • Microprocessors, CPLDs, ASICs, FPGAs, DSPs, etc. • Flash isn’t directly compatible, but programmable

  5. Boundary-Scan Market Drivers • Drivers • Lack of access for testing via conventional methods • Desire to program devices after board assembly • Need for commonality of platforms • Requirement for system-level testing 2000s uBGA 1980s Pin count PLCC 1970s DIP Complexity

  6. TAP controller Boundary-Scan at the Chip Level BR BR BR BR BR BR BR Internal Core Logic • Implemented in the ICs • Adds logic to the chips, allowing data from an external source to be loaded into ... • … and read from the device pins • Accesses a large number of previously unavailable test points • Many of ICs today contain boundary-scan BR BR BR BR TDO TDI Bypass Instruction Reg. ID Register TMS TCK

  7. Applied to the PCB • Board Testing • Scan Infrastructure--verifies the test system and the scan chain • Interconnection -- paths between scan devices • Clusters -- non-scan portions of the board such as edge connectors and other logic • Memory -- address, data, and control lines to memory arrays • In-System Programming • CPLDs--all of the major brands • Flash--all types, at high speed Test Access Port CPLD Flash

  8. 140.0 Programming times of Intel 28F016 16 Mb Flash memory via scan chains at various 130.0 TM shift frequencies using AutoWrite 120.0 110.0 Scan chain consisting of 165 boundary-scan cells @ 12 Volt Vpp 100.0 Scan chain consisting of 165 boundary-scan cells @ 5 Volt Vpp 90.0 Scan chain consisting of 251 boundary-scan cells 80.0 Intrinsic programming time @ Vpp=12 Volt 70.0 Intrinsic programming time @ Vpp=5 Volt 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 FAST FlashProgramming Programming Time (seconds) TCK Frequency (MHz) (Close to theoretical speeds, 1-3 seconds per megabit, depending on board design)

  9. Product Lineup Test: Basic Standard Full Professional Flash Programming: Standard Professional PLD Programming: Standard Full Application Development Packages • Netlist • BSDLs • Cluster Descriptions Application Files UUT Boundary- Scan Controller Production Packages Stand-Alone Server Integration Packages

  10. BOUNDARY-SCAN TEST CHARACTERISTICS • Achievable Fault-coverage • - Infrastructure Test: 100% • - Interconnect Test: 100% • - Memory Interconnection Test: 100% • - Clusters: a) Use PCB SIM (TSSI) w/Active Test • b) Use Active Test w/ golden PCB • Diagnostics – Automatic – To the Pin on the Part at fault! • Test Preparation Time: Much Faster • (5-7 days for most complex designs) • Size of Capital Investments, < ICT Opens Shorts Stuck 0/1 Wrong/Missing Components Pin-Level Shorted Nets Components

  11. Overcomes the Access Problem Simple TAP interface vs. parallel test points Detects Structural PCB Defects Shorts, Opens, Missing Components, Stuck 0/1 Connector, cluster, memory interconnection testing possible Automated Test Pattern Generation and Diagnostics Coverage Can be High, Depending on Scannable Parts The Power of Boundary-Scan Testing

  12. Can provide significant savings Allows test access to complex SMT boards Integrates development, manufacturing, test, and programming Simplifies inventory management, reduces device handling Optimizes use of expensive ATE equipment Less complex ATE and/or test fixtures Rapid test and programming development Summary of Benefits

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