Binary Coded Decimal

# Binary Coded Decimal

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## Binary Coded Decimal

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1. COMPUTER ARITHMETIC Binary Coded Decimal Presented By Chung Wai Chow

2. Binary Coded Decimal Introduction: Although binary data is the most efficient storage scheme; every bit pattern represents a unique, valid value. However, some applications may not be desirable to work with binary data. For instance, the internal components of digital clocks keep track of the time in binary. The binary value must be converted to decimal before it can be displayed.

3. Binary Coded Decimal Because a digital clock is preferable to store the value as a series of decimal digits, where each digit is separately represented as its binary equivalent, the most common format used to represent decimal data is called binary coded decimal, or BCD.

4. Explanation of Binary Coded Decimal (BCD): The BCD format Algorithms for addition Algorithms for subtraction Algorithms for multiplication Algorithms for division

5. 1) BCD Numeric Format • Every four bits represent one decimal digit. • Use decimal values from 0 to 9

6. 1) BCD Numeric Format • 4-bit values above 9 are not used in BCD. The unused 4-bit values are:

7. 1) BCD Numeric Format Multi-digit decimal numbers are stored as multiple groups of 4 bits per digit.

8. 1) BCD Numeric Format • BCD is a signed notation • positive or negative. For example, +27 as 0(sign) 0010 0111. -27 as 1(sign) 0010 0111. • BCD does not store negative numbers in two’s complement.

9. 1) BCD Numeric Format

10. 2) Algorithms for Addition • 1100 is not used in BCD.

11. 2) Algorithms for Addition Two errors will occurs in a standard binary adder. The result is not a valid BCD digit. A valid BCD digit, but not the correct result. Solution: You need to add 6 to the result generated by a binary adder.

12. 2) Algorithms for Addition A simple example of addition in BCD. 5 + 9 Incorrect BCD digit Add 6 Correct answer 0101 + 1001 1110 + 0110 10100 1 4

13. 2) Algorithms for Addition A BCD adder 0101 1001 If the result, S3 S2 S1 S0, is not a valid BCD digit, the multiplexer causes 6 to be added to the result. 0001 = 1 0100 = 4

14. 3) Algorithms for Subtraction A simple example of subtraction 0111 + 1101 0100 (+7) (- 3) (+4) 0011 is 3, the one’s complement is 1100. Each of the computations adds 1 to the one’s complement to produce the two’s complement of the number. 1100 + 1 = 1101 The two’s complement of 3 is 1101

15. 3) Algorithms for Subtraction • The second change has to do with complements. • The nine’s complement in BCD, generated by subtracting the value to be complemented from another value that has all 9S as its digits. Adding one to this value produces the ten’s complement, the negative of the original value. e.g, the nine’s complement of 631 is 999 – 631 = 368. 368 + 1 = 369 is the ten’s complement

16. 3) Algorithms for Subtraction • The ten’s complement plays the subtraction and negation for BCD numbers. Hareware generates the nine’s complement of a single BCD digit.

17. Conclusion for addition and subtraction Using a BCD adder and Nine’s complement generation hardware to compute the addition and the subtraction for signed-magnitude binary numbers The algorithm for adding and subtracting as below: PM’1: US XS, CU X + Y PM1: CU X + Y’ + 1, OVERFLOW 0 PM’2: OVERFLOW C

18. The algorithm for adding and subtracting 2: FINISH 1 CZ’PM2: US XS CZPM2: US 0 C’PM2: US X’S, U U’ + 1

19. Example of addition of BCD numbers USU = XSX + YSY XSX = +33 = 0 0011 0011 YSY = +25 = 0 0010 0101 PM’1: US 0, CU 0 0101 1000 PM’2: OVERFLOW 0 Result: USU = 0 0101 1000 = +58

20. Example of subtraction of BCD numbers USU = XSX + YSY XSX = +27 = 0 0010 0111 YSY = -13 = 1 0001 0011 PM1: CU 1 0001 0100, OVERFLOW 0 CZ’PM2: US 0 Result: USU = 0 0001 0100 = +14

21. 4) Algorithms for Multiplication 1101 Multiplicand M X 1011Multiplier Q 1101 1101 0000 1101____ 10001111 Product P

22. 4) Algorithms for Multiplication Multiplicand Multiplier Product

23. 4) Algorithms for Multiplication Required to use the BCD adder and nine’s complement circuitry. In BCD, each digit of the multiplicand may have any value from 0 to 9; each iteration of the loop may have to perform up to nine additions. We must incorporate an inner loop in the algorithm for these multiple additions. In addition, use decimal shifts right operation (dshr), which shift one BCD digit, or four bits at a time.

24. 4) Algorithms for Multiplication The BCD multiplication algorithm 1: US XS+YS, VS XS+YS,U 0, i n, Cd 0 ZY0’2: CSU CdU + X, Yd0 Yd0 – 1, GOTO 2 ZY02: i i - 1 3: dshr (CdUV), dshr(Y) Z’3: GOTO 2 ZT3: US 0, VS 0 Z3: FINISH 1

25. 4) Algorithms for Multiplication

26. 5) Algorithms for Division Division can be implemented using either a restoring or a non-restoring algorithm. An inner loop to perform multiple subtractions must be incorporated into the algorithm. 10 11 ) 1000 11_ 10

27. 5) Algorithms for Division A logic circuit arrangement implements the restoring-division technique

28. A restoring-division example Initially 0 0 0 0 0 1 0 0 0 0 0 0 1 1 Shift 0 0 0 0 1 0 0 0 Subtract 1 1 1 0 1 Set q01 1 1 1 0 Restore 1 1 0 0 0 0 1 0 0 0 0 Shift 0 0 0 1 0 0 0 0 Subtract 1 1 1 0 1 Set q01 1 1 1 1 Restore 1 1 0 0 0 1 0 0 0 0 0 Shift 0 0 1 0 0 0 0 0 Subtract 1 1 1 0 1 Set q00 0 0 1 0 0 0 0 1 Shift 0 0 0 1 0 0 0 1 Subtract 1 1 1 0 1 Set q01 1 1 1 1 Restore 1 1 0 0 0 1 0 0 0 1 0 First cycle Second cycle Third cycle Fourth cycle Quotient remainder

29. 5) Algorithms for Division The restoring-division algorithm: S1: DO n times Shift A and Q left one binary position. Subtract M from A, placing the answer back in A. If the sign of A is 1, set q0 to 0 and add M back to A (restore A); otherwise, set q0 to 1.

30. 5) Algorithms for Division The non-restoring division algorithm: S1: Do n times If the sign of A is 0, shift A and Q left one binary position and subtract M from A; otherwise, shift A and Q left and add M to A. S2: If the sign of A is 1, add M to A.

31. References: Computer Systems Organization & Architecture, Addison Wesley Longman, Inc., 2001 Introduction to Computer Organization 4th Edition. V.Carl hamacher. 1998 http:// www.sfxavier.ac.uk/computing/bcd/bcd1.htm http:// www.awl.com/carpinelli Thank you