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Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-bit Parallel Adder

Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-bit Parallel Adder. Babu, H. M. H. Chowdhury, A.R, “Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder,” 18th International Conference on VLSI Design, pp. 255 - 260, 2005.

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Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-bit Parallel Adder

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  1. Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-bit Parallel Adder Babu, H. M. H. Chowdhury, A.R, “Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder,” 18th International Conference on VLSI Design, pp. 255 - 260, 2005. Advisor : Dr . Shu-Chung Yi Author : Shi-Xun Chang

  2. Outline 1 . Introduction 2 . Synthesis algorithm of the propose circuit 3 . Full-design of the propose BCD adder 4 . Conclusions

  3. Introduction This paper has proposed a design technique for the reversible circuit of Binary Coded Decimal adder . The proposed circuit has the ability to add two 4-bits binary variables and it transforms the addition into the appropriate BCD number with efficient error correcting modules where the operations are reversible .

  4. Synthesis algorithm of the propose circuit Construct a reversible full-adder circuit efficiently so that the circuit requires very few numbers of gates and generates small number of garbage outputs.

  5. Synthesis algorithm of the propose circuit Construct a reversible 4 bits parallel adder by cascading four copies of reversible full-adder circuits .

  6. Synthesis algorithm of the propose circuit Construct necessary combinational logic to control overflow of the result of addition by selecting appropriate reversible gates .

  7. Synthesis algorithm of the propose circuit Apply two 4 bits operands (A 3A 2A 1A 0 and B 3B 2B 1B 0) into the first 4 bits reversible adder and generate the initial sum (S 3S 2S 1S 0) and carry C 4 .

  8. Synthesis algorithm of the propose circuit Apply the result into the combinational logic for error correction .

  9. Synthesis algorithm of the propose circuit Apply the initial sum (S 3S 2S 1S 0) into the first four pins of the second reversible 4-bits parallel adder and error correcting code into the last four pins to get the final addition .

  10. Full-design of the propose BCD adder

  11. Conclusions The proposed BCD adder circuit can further be used in a large reversible system as a module of reversible logic .In future , we have the plan to construct large reversible system that executes more than one reversible operations concurrently .

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