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EE 367 Logic Design

This lecture discusses essential tools for Logic Design in EE 367, focusing on MS Visio for schematic creation, ModelSim for HDL simulation (supporting VHDL and Verilog), and Xilinx ISE for FPGA implementation. MS Visio helps in crafting clean schematics with built-in shape libraries, while ModelSim features color-coded text editing and verification reporting. Xilinx ISE is pivotal for compiling, simulating, and synthesizing designs, offering comprehensive features from technology mapping to timing verification and programming. Key class updates include no class on Martin Luther King Jr. Day.

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EE 367 Logic Design

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    1. Lecture #2 Page 1 EE 367 – Logic Design Spring 2008 EE 367 – Logic Design Lecture #2 Agenda Logic Design Tools Announcements (Friday, 1/18) No Class Monday (1/21), MLK Holiday

    2. Lecture #2 Page 2 EE 367 – Logic Design Spring 2008 Logic Design Tools MS Visio - a generic drawing program. - industry is converging on this program for documentation. - has built in shape libraries, including analog/digital logic. - we’ll use it for this class to create clean schematics.

    3. Lecture #2 Page 3 EE 367 – Logic Design Spring 2008 Logic Design Tools MS Visio

    4. Lecture #2 Page 4 EE 367 – Logic Design Spring 2008 Logic Design Tools ModelSim (by Mentor Graphics) - an HDL Simulation (VHDL and Verilog) - widely used in industry - has color-coded text editing for keywords - has console for verification reporting - we’ll use for homework & before FPGA synthesis.

    5. Lecture #2 Page 5 EE 367 – Logic Design Spring 2008 Logic Design Tools ModelSim

    6. Lecture #2 Page 6 EE 367 – Logic Design Spring 2008 Logic Design Tools ModelSim

    7. Lecture #2 Page 7 EE 367 – Logic Design Spring 2008 Logic Design Tools Xilinx ISE - Integrated Software Environment (ISE) - Implementation tool - compile / simulate - synthesis - technology mapping - place and route - back annotation for post-route simulation and timing verification - can do similar simulation as in ModelSim - this is where we : - select FPGA to target - assign signal pins - set timing constraints - set placement constraints - set routing constraints - generate programming file - download file to FPGA, EEprom, or CPLD using the JTAG interface.

    8. Lecture #2 Page 8 EE 367 – Logic Design Spring 2008 Logic Design Tools Xilinx ISE

    9. Lecture #2 Page 9 EE 367 – Logic Design Spring 2008 Logic Design Tools Xilinx ISE

    10. Lecture #2 Page 10 EE 367 – Logic Design Spring 2008 Logic Design Tools Xilinx ISE

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