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FUNDAMENTALS OF MULTICHIP PACKAGING

FUNDAMENTALS OF MULTICHIP PACKAGING. Adeel Baig Jason Shin. Chapter Objectives. Define multichip modules and basic application areas Describe multichip module types and construction Present elements of multichip module design

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FUNDAMENTALS OF MULTICHIP PACKAGING

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  1. FUNDAMENTALS OF MULTICHIP PACKAGING Adeel Baig Jason Shin

  2. Chapter Objectives • Define multichip modules and basic application areas • Describe multichip module types and construction • Present elements of multichip module design • Develop tradeoffs between multichip module types and alternative packaging methods. Microsystems Packaging

  3. 8.1 What Are Multichip Modules? • A single unit (package) containing two or more chips and an interconnection substrate which function together as a system building block. • Classification Requirements • Ac ≥ 0.5 As • Ac is the area of the semiconductor or chip. • As is the area of the substrate (package or carrier)

  4. 8.1 What Are Multichip Modules?

  5. 8.1 What Are Multichip Modules? • Functions • Provide signal interconnect and I/O management • Thermal management • Mechanical support • Environmental protection

  6. 8.1 What Are Multichip Modules? • Advantages • Chips spaced more closely. • Reduced volume and weight. • Applications • Aerospace • Medical • Consumer • Portable • Supercomputers

  7. 8.2 Multichip Module Functionality • For a highly functional MCM, the following criteria must be satisfied: • Chip to chip spacing must be held to a minimum. • The MCM must provide a means of thermal management to limit the junction temperature of the semiconductor chips to less than 85 - 100°C. • The MCM must provide reliable I/O connections to the next level of assembly. • The MCM must provide protection from the environment.

  8. 8.2 Multichip Module Functionality

  9. 8.3 Multichip Module Advantages • Higher packaging efficiency. • Better electrical performance. • Greater reliability. • Potential for lower cost.

  10. 8.3.1 Packaging Efficiency • Packaging efficiency is the ratio of the area of all the base chips to the area of the MCM substrate. • Single chip package efficiency is between 10 – 50%. • MCM package efficiency is around 80%.

  11. 8.3.1 Packaging Efficiency MCM Single Chips

  12. 8.3.2 Electrical Performance • MCM performance can be measured by functional throughput rate (FTR). • FTR is the product of the number of gates per module times the maximum clock rate of such gates. • Maximum clock rate is 0.25tD where tD is the delay associated with the typical gate. • Another measure of performance is MIPS. • Number of MIPS = 103 / [(cycle time) X (cycles per instructions)] • Other measures include clock speed, operation frequency, and power dissipation.

  13. 8.3.3 Reliability • Three different areas: • Design for reliability with a minimum number of connections. • Construct the module using six-sigma manufacturing processes. • Perform accelerated and other screening tests on the MCM to remove defect-induced failures before the product is shipped to the consumer.

  14. 8.3.4 Cost • Cost is expected to be lower than the alternative single chip package implementation. • Reduction of the number of interconnects and minimized substrate area and system volume. • Cost per unit area is higher, but the overall size is smaller.

  15. 8.4 Multichip Modules at the System Level

  16. 8.4.1 Electrical Design • Considerations • Signal paths must be short with controlled impedances and low loss. • Deviations from design specifications can result in crosstalk, increased delays, and distorted signal waveforms. • Must address dielectric constant, signal line geometries, interline spacing, and the distribution and location of power and ground.

  17. 8.4.2 Sealing and Encapsulation • MCMs are either hermetically sealed in ceramic or metal packages or they are encapsulated. • Hermetic sealing or encapsulation of the MCM is important and can contribute to module reliability. • Encapsulants need to be reworkable for high value MCMs. • Encapsulant must be easy to remove.

  18. 8.4.3 Heat Removal • Module power dissipations have risen from a few Watts per module to 30-180 Watts per module. • ICs must be maintained at 100°C or below.

  19. 8.4.3 Heat Removal • Substrate aids in the heat removal process. • Actual thermal transfer depends on how the chips are interconnected to the substrate. • Three methods of interconnect: • Wirebonding • Flip Chip • Tape Automated Bonding (TAB)

  20. 8.4.3 Heat Removal

  21. 8.4.4 Electrical Interconnections • Requirements • Fatigue and creep resistance • Corrosion resistance • Electromigration resistance • High conductivity

  22. 8.4.4 Electrical Interconnections • Wirebonding • Flexible • Low interconnect cost • Lower capitalization cost • Ease of use

  23. 8.4.4 Electrical Interconnections • Flip Chip • Can effect the highest number of interconnects per unit area. • All interconnects are contained within the chip area. • Extremely low capacitance and inductance per joint. • Most robust replacement process.

  24. 8.4.7 Electrical Testing • Different Levels of Testing • Substrates must be defect free prior to assembly. • Verify that all networks are connected appropriately. • Visual inspection. • After assembly, MCM must be electrically tested to ensure that the module is working. • Device must be encapsulated and environmentally stressed. • In an MCM, if one die fails, the whole module fails.

  25. 8.5 Types of Multichip Module Substrates MCM - More than half of its area covered with active devices Move from PWB to MCMs Three basic styles of MCMs MCM-L MCM-C MCM-D Microsystems Packaging

  26. 8.5 Types of Multichip Module Substrates Microsystems Packaging

  27. 8.5.1 MCM-L Organic PWB fabrication Organic coatings used to protect chips and bonds Three types of lamination substrates Rigid Flex Rigid flex Microsystems Packaging

  28. 8.5.1 MCM-L (continued) Two types of dielectric layers in MCM-L construction Cores Prepregs MCM-L substrate process Selecting appropriate core and prepreg layers Photolithographic pattering and etching of copper conductors on the core layers Drilling of vias Lamination of the cores to each other using the prepreg layers. Plating of drilled holes in single layers, partially though several layers and holes all the way though the board Microsystems Packaging

  29. 8.5.1 MCM-L (continued) Inner layer processing Copper surfaces cleaned in preparation for pattern processing Photoresist is applied by laminating of a dry film resist material (other techniques) Liquid resists typically allow finer line definition Pattern is exposed with ultraviolet light – removes unwanted resist areas Copper foil is etched in ammonia-based alkaline system Photoresist is chemically removed Microsystems Packaging

  30. 8.5.1 Advanced MCM-L substrates Advanced MCM-L substrates Cost increases as hole diameter decreases In high density applications (micro processors) loss of wiring density cannot be tolerated Built-up technology Microsystems Packaging

  31. 8.5.1 Advanced MCM-L substrates Microsystems Packaging

  32. 8.5.2 MCM-C Ceramic-based substrates Evolved from traditional thick-film fabrication techniques Density increased: Shrinking size of features (vias) used for interconnecting layers Shrinking conductor traces used for signal routing Shrinking gaps between traces or vias Microsystems Packaging

  33. 8.5.2 MCM-C (continued) MCM-C Process Dielectric layers are sheets of unfired ceramic green state ceramic Each sheet is separately patterned Vias are mechanically punched or laser drilled Vias filled by extruding the conducting paste into the holes though a stencil Fired Microsystems Packaging

  34. 8.5.2 MCM-C (continued) Microsystems Packaging

  35. 8.5.2 MCM-C (continued) 2 –types High temperature cofired ceramic (HTCC) Low temperature cofired ceramic (LTCC) Microsystems Packaging

  36. 8.5.2 MCM-D Combination of superior materials and dimensional resolving power of thin-film technology Several dielectric/metallization technologies Vias are formed in the polyimide by reactive-ion etching in an oxygen plasma using a photo-patterned metal mask Microsystems Packaging

  37. 8.5.2 MCM-D Microsystems Packaging

  38. 8.6 Multichip Module Design Wireability analysis used to find the basic size possible Basic concepts Estimation of wiring demand Wiring capacity Average wire length Connectivity Microsystems Packaging

  39. 8.6 Multichip Module Design (continued) Wiring demand (D) amount of wiring required to interconnect a given circuit Wiring capability (C) is the amount of wiring available for interconnection Wiring efficiency 30-70% range depending on circuit type Microsystems Packaging

  40. 8.6 Multichip Module Design (continued) Wiring capacity Function of the minimum signal line pitch Ps that can be fabricated on a given MCM substarate technology. Total wiring capacity: Microsystems Packaging

  41. 8.6 Multichip Module Design (continued) Wiring demand Wire demand without preliminary layout requirements Microsystems Packaging

  42. 8.7 Multichip module technology comparisons Microsystems Packaging

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