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Logic Reversibility in Reduced Ordered Binary Decision Diagrams

This project investigates the determination of logic reversibility in Reduced Ordered Binary Decision Diagrams (ROBDDs). It includes a module-based interpreter for function development and offers a direct mapping to and from PLA and SPEC files. Key achievements involve demonstrating a logic synthesis algorithm, generating BDD graphs, and detecting input types. The research also discusses outstanding issues like generating reversible functions and optimizing incompletely specified functions. Future work focuses on addressing these issues and enhancing performance, especially for larger variable sets.

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Logic Reversibility in Reduced Ordered Binary Decision Diagrams

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  1. Determination of Logic Reversibility in Reduced Ordered Binary Decision Diagrams Zakaria Hamza CS6805: Logic Synthesis Final Project Professor: Dr. Gerhard Dueck

  2. Outline • Achieved Goals • Milestones of Project • Outstanding Issues • Results • Logic Synthesis Algorithm • Discussions and Conclusion Zakaria Hamza CS6805: Logic Synthesis Final Project

  3. Achieved Goals • Determination of basic function properties: • Tautological • Reversible • Contradictory • Module-based interpreter included for function development • Ability to map to and from PLA and SPEC files directly • BDD graph generation Zakaria Hamza CS6805: Logic Synthesis Final Project

  4. Achieved Goals • Demonstration of the logic synthesis algorithm: • Detect input type • Use fastest algorithm to derive properties of a binary function and output • 1st image: sample dual variable ROBDD • 2nd image: sample truth table derived from specification and PLA file. Zakaria Hamza CS6805: Logic Synthesis Final Project

  5. Milestones of Project : Pending : Completed Zakaria Hamza CS6805: Logic Synthesis Final Project

  6. Outstanding Issues • Generate reversible functions from logic function specifications • Determine if patterns are found within functions: • Transitivity • Symmetry • Simplification patterns • Decide best option to analyze any given PLA/SPEC configuration • Optimize incompletely specified functions Zakaria Hamza CS6805: Logic Synthesis Final Project

  7. Results (Runtime) • Java-Based Logic Engine: • Cross-platform (requires 1.4.2 or newer) • Compatible with UNIX command line based packages (i.e.: CUDD) • Includes powerful source code for handling BDD structures using JDD • Relies on a virtual machine and does not drivers or platform specific features • Uses system calls if available Zakaria Hamza CS6805: Logic Synthesis Final Project

  8. Results (Toolbox) • Includes C and POSIX command line verification programs • PLA and SPEC interchangeability • Programmed adaptability to GraphViz based graph data structures (for large numbers of variables) • Supports modifying logic functions • Determines if a function is reversible or could be made reversible using an exponential algorithm Zakaria Hamza CS6805: Logic Synthesis Final Project

  9. Results (GUI) • Planned support for modification of Karnaugh maps, Toffoli networks, BDD and other logic display formalisms • Allow user input and interaction with display formalism structures • UI engine used to define customizable operations and functions • Toolbox is integrated with UI Zakaria Hamza CS6805: Logic Synthesis Final Project

  10. Logic Synthesis Algorithm • Input PLA/SPEC/BDD data structures • Use dynamic programming to analyze function and generate as much information about it as possible • Module section for specific functionality • Reversibility • Simplification/Reduction • Contradiction • Quine-McCluskey/SAT/Circuit optional (brute force) algorithms, etc. • Create BDD • Convert to ROBDD • User interface manual specifications (inherited functions from Quiver/RevLib as well) • Heuristic algorithm to generate output function or graph Zakaria Hamza CS6805: Logic Synthesis Final Project

  11. Further Works • Resolve outstanding issues (further developing a thesis base) • Optimize code for better performance and increased range of operability • Use sparse matrices to store truth tables • Optimize algorithm runtime for large numbers of variables (>20) or use hardware with larger addressing modes Zakaria Hamza CS6805: Logic Synthesis Final Project

  12. Discussions and Conclusions • Current algorithm consumes exponential resources relative to the number of input variables • Functions may or may not terminate depending on how effectively virtual memory is used • Storing large truth tables is simply infeasible and a graph structure is almost indispensable • Tree-based compression structures may reduce runtime dramatically if properly encoded Zakaria Hamza CS6805: Logic Synthesis Final Project

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