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HDLC controller for EC/ECP

HDLC controller for EC/ECP. Index HDLC description - The OSI Stack Protocol model - Communication of Layer2 - HDLC Frame format - Protocols that use HDLC framing Block diagram of Single HDLC controller - Block diagram for single channel - Rx black diagram - Tx black diagram

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HDLC controller for EC/ECP

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  1. HDLC controller for EC/ECP

  2. Index • HDLC description - The OSI Stack Protocol model - Communication of Layer2 - HDLC Frame format - Protocols that use HDLC framing • Block diagram of Single HDLC controller - Block diagram for single channel - Rx black diagram - Tx black diagram • Timing diagram

  3. HDLC Frame Format

  4. Block Diagram of HDLC controller EC/ECP Line Framer CPU Rx HDLC Rx FIFO Rx Control Logic CPU I/F Tx Control Logic Tx HDLC Tx FIFO Tx Modification Logic Data line

  5. HDLC_Controller_Rx • HDLC_RECEIVE_CCITT (x16 + x15 + x5 + 1) • HDLC_RECEIVE_CRC16 (x16 + x15 + x2 + 1) • HDLC_RECEIVE_CRC32 • (x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1)

  6. Rx Block diagram for single channel Rx control Rx HDLC Controller RxStatusWrite_n RxClk RxOutputData Rd_data RxData Q[7:0] Data[7:0] RxDataWrite_n Rden_cpu Rden Wren RxClk Cpu_clock WrClock RdClock Reset Reset Full Almost Full Empty Almost Empty

  7. HDLC_Controller_Tx • HDLC_TRANSMIT_CCITT (x16 + x15 + x2 + 1) • HDLC_TRANSMIT_CRC16 (x16 + x15 + x2 + 1) • HDLC_TRANSMIT_CRC32 • (x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1)

  8. Tx Block diagram for single channel Tx_Abort Tx Control Tx HDLC Controller Tx_Empty CPU_CS WREN Tx_Start Tx FIFO Memory CPU_Data Tx_data Q[7:0] Data[7:0] CPU_WREN TxRead_n Rden Wren Cpu_clock Rx_clk WrClock RdClock Reset Full Reset Almost Full Empty Almost Empty

  9. 1 F 7 E 7 E Tx Modification for accommodating HDLC format with SCC 1 1 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 5 F 7 E 7 E 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 9 F 7 E 7 E 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 C F 7 E 7 E FCS Flag When the last FCS byte is hx1F, hx9F, hx3F, hxEF, Tx data modulation is needed to avoid abort alarm in PowerPC SCC port

  10. 1 1 F F 3 7 F E 7 7 E E 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 FCS Modified Flag Flag Tx Modification for accommodation with SCC 1 1 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 Abort Alarm is occurred in SCC port FCS Flag Flag Whenever there are five consecutive 1’s followed by a zero, the zero will be ignored in PowerPC SCC port. So the zero which is located between FCS and Flag is ignored and SCC port recognized Abort status To avoid Abort status, Modified flag is need

  11. Modification source code Process(RST, CLK, Int0_reg) begin if rst = '0' then Int0_reg <= ( others => '0'); elsif CLK'event and CLK = '0' then if (Int0_reg(14 downto 0) = "011111011111100") then Int0_reg(16 downto 0) <= int0_reg(15) & "011111001111110" & txdata0a; else Int0_reg(16 downto 0) <= Int0_reg(15 downto 0) & txdata0a; end if; end if; end process; Txdata0 <= Int0_reg(16);

  12. Timing diagram of HDLC controller CPU writes a data to Tx_FIFO CPU reads a data from Rx_FIFO Interrupt signal for end of frame HDLC writes a data to Rx_FIFO HDLC reads a data from Tx_FIFO data FCS

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