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OCP-IP Governing Steering Committee Meeting June 24, 2010

OCP-IP Governing Steering Committee Meeting June 24, 2010.

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OCP-IP Governing Steering Committee Meeting June 24, 2010

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  1. OCP-IPGoverning Steering Committee MeetingJune 24, 2010

  2. 07:00- 07:15 AM: Call to Order, Introductions, Agenda Review, Last Minutes - Record Metadata Vendor Extensions electronic vote (Ian)07:15- 07:25 AM: Next GSC Meeting (Ian)07:25- 07:45 AM: Metadata WG Update (Prashant) - Schedule Update for agreed goals 07:45- 08:05 AM: System Level Design WG Update (Mark/James) - Schedule Update for agreed goals - Circuit Sutra’s workplan, schedule, status and progress - OCP 3.0 Support Update08:05- 08:25 AM: NoC BWG Update (Erno) - Schedule Update for agreed goals 08:25- 08:35 AM: Motion to Adjourn/ Break/ Reconvene 08:35- 08:55 AM: FVWG Discussion (Gabriele) - Schedule Update for agreed goals 08:55- 09:15 AM: Debug WG Update (Bob) - Schedule Update for agreed goals

  3. 09:15- 09:35 AM: Specification WG Status (Drew) - Schedule Update for agreed goals - Schedule / Participation OCP 4.0 (Drew)09:35- 09:45 AM: Technical Vision WG Status / Restated (Ian) 09:45- 10:05 AM: Progress in Asia (Ian) 10:05- 10:15 AM: Motion to Adjourn/ Break/ Reconvene 10:15- 11:15 AM: AI Review (Ian) 11:15- 11:35 PM: PR Update (Joe) 11:35- 11:45 PM: Recruiting Update (Joe) 11:45- 12:00 PM: Budget/Cash Flow Update (Ian) - 2010 budget update12:00- 12:20 PM: Administrative Update (VitalCom) 12:20- 12:25 PM: Enabling Resolution (Ian)12:25- 12:30 PM: Motion to Adjourn Lunch

  4. Call to Order and Agenda Review (Ian) • Call to Order • Welcome from the President • Review Agenda • Any additional items?

  5. Vote to Approve Last GSC Meeting Minutes • 33rd GSC Meeting • March 04, 2010 via teleconference

  6. 07:00- 07:15 AM: Call to Order, Introductions, Agenda Review, Last Minutes - Record Metadata Vendor Extensions electronic vote (Ian)07:15- 07:25 AM: Next GSC Meeting (Ian)07:25- 07:45 AM: Metadata WG Update (Prashant) - Schedule Update for agreed goals 07:45- 08:05 AM: System Level Design WG Update (Mark/James) - Schedule Update for agreed goals - Circuit Sutra’s workplan, schedule, status and progress - OCP 3.0 Support Update08:05- 08:25 AM: NoC BWG Update (Erno) - Schedule Update for agreed goals 08:25- 08:35 AM: Motion to Adjourn/ Break/ Reconvene 08:35- 08:55 AM: FVWG Discussion (Gabriele) - Schedule Update for agreed goals 08:55- 09:15 AM: Debug WG Update (Bob) - Schedule Update for agreed goals

  7. Call for motion to release Meta Data Vendor Extensions April 19, 2010 GSC approved release April 21, 2010 Kit made available May 10, 2010 Press Release announcing availability on May 10th Record Electronic Vote for Metadata Vendor Extensions 7

  8. 07:00- 07:15 AM: Call to Order, Introductions, Agenda Review, Last Minutes - Record Metadata Vendor Extensions electronic vote (Ian)07:15- 07:25 AM: Next GSC Meeting (Ian)07:25- 07:45 AM: Metadata WG Update (Prashant) - Schedule Update for agreed goals 07:45- 08:05 AM: System Level Design WG Update (Mark/James) - Schedule Update for agreed goals - Circuit Sutra’s workplan, schedule, status and progress - OCP 3.0 Support Update08:05- 08:25 AM: NoC BWG Update (Erno) - Schedule Update for agreed goals 08:25- 08:35 AM: Motion to Adjourn/ Break/ Reconvene 08:35- 08:55 AM: FVWG Discussion (Gabriele) - Schedule Update for agreed goals 08:55- 09:15 AM: Debug WG Update (Bob) - Schedule Update for agreed goals

  9. 35th GSC Meeting Should this be via Teleconference or at T.I.? Timing around week of September 27th? (Proposed September 30th) Start Time? Next GSC Meeting (Ian) 9

  10. 07:00- 07:15 AM: Call to Order, Introductions, Agenda Review, Last Minutes - Record Metadata Vendor Extensions electronic vote (Ian)07:15- 07:25 AM: Next GSC Meeting (Ian)07:25- 07:45 AM: Metadata WG Update (Prashant) - Schedule Update for agreed goals 07:45- 08:05 AM: System Level Design WG Update (Mark/James) - Schedule Update for agreed goals - Circuit Sutra’s workplan, schedule, status and progress - OCP 3.0 Support Update08:05- 08:25 AM: NoC BWG Update (Erno) - Schedule Update for agreed goals 08:25- 08:35 AM: Motion to Adjourn/ Break/ Reconvene 08:35- 08:55 AM: FVWG Discussion (Gabriele) - Schedule Update for agreed goals 08:55- 09:15 AM: Debug WG Update (Bob) - Schedule Update for agreed goals

  11. Meta Data WG Update Prashant Karandikar(Texas Instruments), June 24, 2010

  12. Metadata WG Status

  13. Spirit Interoperability Implement OCP within existing spirit format Use the Magillem/Sonics proposal as basis ST-style checking is used to validate an IP description Add Abstraction Definition files for OCP TL1/2/3 abstraction sockets Status : Package released to OCP-IP Members for RTL level of abstraction Abstraction Definition files for OCP TL1/2/3 level of abstraction to be put together 13

  14. Spirit Enhancement Propose and drive modifications into IP-XACT standard Waiting for Accellera Working Group on IP-XACT standardization to be formed. 14

  15. Core Compatibility report Ability to automatically compare OCP interface configurations Check the inter-interface consistency (Current configuration compliance checks) Check consistency of a connected master / slave interface pair (Current interface interoperability checks) Check consistency of the ports and parameters Generate the rtl.conf file out of configured IP-XACT parameter list (legacy support) Configure IP-XACT parameter list based on an rtl.conf file and give rtl.conf files of OCP standard profiles as examples (legacy support) Status Consistency of ports & parameters checker delivered as part of the MDWG package First version of the interface checker have been send to MDWG. rtl.conf  IP-XACT ( legacy support ) discussed and agreed. 15

  16. OCP3.0 Add OCP 3.0 signals and parameters to bus definition schema Status MDWG started study of the final version of OCP3.0 spec. 16

  17. 07:00- 07:15 AM: Call to Order, Introductions, Agenda Review, Last Minutes - Record Metadata Vendor Extensions electronic vote (Ian)07:15- 07:25 AM: Next GSC Meeting (Ian)07:25- 07:45 AM: Metadata WG Update (Prashant) - Schedule Update for agreed goals07:45- 08:05 AM: System Level Design WG Update (Mark/James) - Schedule Update for agreed goals - Circuit Sutra’s workplan, schedule, status and progress - OCP 3.0 Support Update08:05- 08:25 AM: NoC BWG Update (Erno) - Schedule Update for agreed goals 08:25- 08:35 AM: Motion to Adjourn/ Break/ Reconvene 08:35- 08:55 AM: FVWG Discussion (Gabriele) - Schedule Update for agreed goals 08:55- 09:15 AM: Debug WG Update (Bob) - Schedule Update for agreed goals

  18. SLD Working Group Update Mark Burton (Greensocs), June 24, 2010

  19. Summary • Platform release still held up. • Agreement with Larry/ Umesh should be tied up this week. • Mark Burton has now moved to Windriver (Intel), working on getting Intel membership of OCP. Currently in Legal.

  20. Other work in the WG: Not Much! • Currently we are seriously struggling. There is no longer much GreenSocs resource. TI and Sonics provide some, but can not make major contributions.

  21. SLD WG Status

  22. The SLD Mid-Term Vision - unchanged • OUR KIT IS HIGH QUALITY, AND STABLE.. • Ensure that OCP users have a 'complete' modelling infrastructure available • multiple levels of abstraction (pure-functional to cycle-accurate) and use models (software development, architecture exploration, etc) • completeness means • bus interface , performance monitoring interface ,system debug interface and configuration interface • Make this modelling infrastructure standards compliant. • E.g. drive existing OCP-IP experience and expertise into OSCI-TLM • Maintain alignment between OSCI-TLM OCP-IP

  23. 07:00- 07:15 AM: Call to Order, Introductions, Agenda Review, Last Minutes - Record Metadata Vendor Extensions electronic vote (Ian)07:15- 07:25 AM: Next GSC Meeting (Ian)07:25- 07:45 AM: Metadata WG Update (Prashant) - Schedule Update for agreed goals 07:45- 08:05 AM: System Level Design WG Update (Mark/James) - Schedule Update for agreed goals - Circuit Sutra’s workplan, schedule, status and progress - OCP 3.0 Support Update08:05- 08:25 AM: NoC BWG Update (Erno) - Schedule Update for agreed goals 08:25- 08:35 AM: Motion to Adjourn/ Break/ Reconvene 08:35- 08:55 AM: FVWG Discussion (Gabriele) - Schedule Update for agreed goals 08:55- 09:15 AM: Debug WG Update (Bob) - Schedule Update for agreed goals

  24. NoC Benchmarking WG Update Erno Salminen(Tampere University Technology), June 24, 2010

  25. NoC Benchmarking WG Status

  26. Recent activities First part of TG modifications completed Simpler installation OSCI TLM Mixed-language simulation with VHDL+SystemC demonstrated Includes basic mesh NoC in VHDL and SystemC TG was used in teaching during spring succesfully TG release is currently at GSC voting 26

  27. Recent activities (2) Krishnan Srinivasan (Sonics) started working on guideline article how to model memories Srini has plan but has been waiting for an approval from his superiors for several weeks Just in case there are some IP issues (?) Article about workgroup’s goals and outcomes so far Probably 2-4 pages By TUT + KTH, during June-July 27

  28. Next actions Second part of Transaction Generator updates Start using OCP-IP TLM kit Tutorial Finalize integration with graphical monitoring support Traffic models for TG by all members 28

  29. Next actions (were ”next” also in March) Profiling of EEMBC MultiBench The work ENSTA seems be going nowhere They promised a document by end of May and nothing came, no replies to emails TUT folks will try this out during summer Available human resources unknown/limited Recruiting new people Two inquiries so far did not succeed by all workgroup members 29

  30. 07:00- 07:15 AM: Call to Order, Introductions, Agenda Review, Last Minutes - Record Metadata Vendor Extensions electronic vote (Ian)07:15- 07:25 AM: Next GSC Meeting (Ian)07:25- 07:45 AM: Metadata WG Update (Prashant) - Schedule Update for agreed goals 07:45- 08:05 AM: System Level Design WG Update (Mark/James) - Schedule Update for agreed goals - Circuit Sutra’s workplan, schedule, status and progress - OCP 3.0 Support Update08:05- 08:25 AM: NoC BWG Update (Erno) - Schedule Update for agreed goals08:25- 08:35 AM: Motion to Adjourn/ Break/ Reconvene 08:35- 08:55 AM: FVWG Discussion (Gabriele) - Schedule Update for agreed goals 08:55- 09:15 AM: Debug WG Update (Bob) - Schedule Update for agreed goals

  31. Break

  32. 07:00- 07:15 AM: Call to Order, Introductions, Agenda Review, Last Minutes - Record Metadata Vendor Extensions electronic vote (Ian)07:15- 07:25 AM: Next GSC Meeting (Ian)07:25- 07:45 AM: Metadata WG Update (Prashant) - Schedule Update for agreed goals 07:45- 08:05 AM: System Level Design WG Update (Mark/James) - Schedule Update for agreed goals - Circuit Sutra’s workplan, schedule, status and progress - OCP 3.0 Support Update08:05- 08:25 AM: NoC BWG Update (Erno) - Schedule Update for agreed goals 08:25- 08:35 AM: Motion to Adjourn/ Break/ Reconvene 08:35- 08:55 AM: FVWG Discussion (Gabriele) - Schedule Update for agreed goals 08:55- 09:15 AM: Debug WG Update (Bob) - Schedule Update for agreed goals

  33. Functional Verification WG Update Gabriele Zarri(Cadence), June 24, 2010

  34. FVWG Discussion (Gabriele) General items : • Continuing the activity started Nov 18th • Forecasted bi-weekly on Weds at 7.30am PT • Attending companies : Cadence, Synopsys, MIPS, TI and Sonics • Quorum usually reached 34

  35. FVWG Discussion (Gabriele) Technical items : Continuing activity on Cache-Coherence extension at different levels : configuration, signals, transfers. Already identified most of the signal and configuration checks. Moving to the transfer checks. List of ‘intervention checks’ already provided by MIPS under analysis. Latency bounds proposal sent to TI, waiting for their feedback. 35

  36. Functional Verification WG Status

  37. 07:00- 07:15 AM: Call to Order, Introductions, Agenda Review, Last Minutes - Record Metadata Vendor Extensions electronic vote (Ian)07:15- 07:25 AM: Next GSC Meeting (Ian)07:25- 07:45 AM: Metadata WG Update (Prashant) - Schedule Update for agreed goals 07:45- 08:05 AM: System Level Design WG Update (Mark/James) - Schedule Update for agreed goals - Circuit Sutra’s workplan, schedule, status and progress - OCP 3.0 Support Update08:05- 08:25 AM: NoC BWG Update (Erno) - Schedule Update for agreed goals 08:25- 08:35 AM: Motion to Adjourn/ Break/ Reconvene 08:35- 08:55 AM: FVWG Discussion (Gabriele) - Schedule Update for agreed goals08:55- 09:15 AM: Debug WG Update (Bob) - Schedule Update for agreed goals

  38. Debug WG Update Bob Uvacek(Samplify), June 24, 2010

  39. OCP-IP Debug Interface Standard Group • Samplify Bob Uvacek, chair • HDL Dynamics Neal Stollon • TI Gilbert Laurenti • Toshiba CY Pei • OCP-IP contacts Ian Mackintosh, Beth Covey, Joe Basques Reviewing members • Nexus Neal Stollon • GreenSocs Mark Burton • Cadence Mike Young, Ran Avinun • MIPI Rolf Kuehnis, Gary Swoboda • ITRI / Global Unichip Alan Su, Prof. Lee, • SPIRIT / Accellera Neal Stollon, Debug-WG Chair Anthony Berent, ARM • PLS / Infineon / SPRINT Jens Braunes, Albrecht Mayer • Tensilica Bruce Ableidinger, Grant Martin 39

  40. OCP-IP Debug Interface Standard Roadmap 3 4 5 6 7 8 9 10 11 12 Ongoing: Promote and present OCP debug slides in shows and journals Extract OCP 3.0 novelties, power and cache, into OCP 1.0 Debug Standard Physical Specification, Include waveforms for OCP signals Write Debug Chapters for new Power and Cache signals Propose processor classification and match to debug complexity levels Survey present market of OCP compliant debug IP. Who invests. Publish it inside OCP for greater review. --------------------------------------------------------- Searching for new points of engagement with industry and universities Who uses heterogeneous multi-processors? Applications? Biggest barrier to OCP debug IP dissemination is processor debug interface variability, and 6 months 2 men adaptation time. 2010 40

  41. Debug WG Status

  42. OCP-IP Debug Interface Standard; New Developments • We see on the market that debug hardware is being used in novel ways with highly complex chips: • - Use debug hardware for PERFORMANCE MEASUREMENT ; • without changing timing of application software: • % bus utilization; number of memory access clashes; number of powered-down blocks; • peak number of outstanding transfers; … (like task monitor in Windows but for OCP buses) • Use debug hardware to create ASSERTION TRIGGERS for events or timing measurement. • Assertions usually report errors. Assertions in debug report any basic events of interest • reusing the modern built-in infrastructure for assertions. • True debug hardware is orthogonal to chip execution and can serve as a “LOGIC ANALYSER” on chip. • Question to think about: • To promote assertions with OCP would it be good time to standardize a few basic assertions • typical for the OCP interface specially for debug to allow debug tools and ESL tools to include • displays and responses to debug assertion signals? 42

  43. Other Debug Activities  Bought by Accelera SPRINT GreenSocs IP-XACT ESL SPIRIT MC Ass. P1687 - IJTAG 1149.7 - CJTAG RTL ITRI 43 Government Invests

  44. Evolution of Multi-Core Debugging and Link to OCP OCP Debug WG GOAL: Commercially available multi-core debug IP-blocks for the OCP interconnect MCDS debug IP takes 12 man months to adapt to a new processor core. Biggest obstacle is the wide variability of the debug interfaces in the processors. We plan to classify processors according to debug interface functionality: Single threaded, multi threaded, outstanding transactions, out of order, cache coherency transactions, … require different debug activities. And absolutely nice would be to see somebody using it with success. 44

  45. 45

  46. Summary Main target philosophy is: Debug N cores on a chip by selecting any 2 or more cores for a time-aligned comparative debug session. OCP-IP has standardized a Debug Interface between system bus and multiple processor cores and IP-blocks in a SoC design. • It enables reusable multi-core Debug-Hardware solutions. (OCP/JTAG/Nexus/MIPI)‏ • It promotes Debug-Software for multiple cores in one GUI. (See SPRINT debug APIs)‏ • This shall create the market for SoC designers for reuse of verified multi-core debug-IP solutions. (See IP-Extreme, HDL-Dynamics, Temento, ... IP providers)‏ 46

  47. 09:15- 09:35 AM: Specification WG Status (Drew) - Schedule Update for agreed goals - Schedule / Participation OCP 4.0 (Drew)09:35- 09:45 AM: Technical Vision WG Status / Restated (Ian) 09:45- 10:05 AM: Progress in Asia (Ian) 10:05- 10:15 AM: Motion to Adjourn/ Break/ Reconvene 10:15- 11:15 AM: AI Review (Ian) 11:15- 11:35 PM: PR Update (Joe) 11:35- 11:45 PM: Recruiting Update (Joe) 11:45- 12:00 PM: Budget/Cash Flow Update (Ian) - 2010 budget update12:00- 12:20 PM: Administrative Update (VitalCom) 12:20- 12:25 PM: Enabling Resolution (Ian)12:25- 12:30 PM: Motion to Adjourn Lunch

  48. Specification WG Update Drew Wingard(Sonics Inc), June 24, 2010

  49. Specification WG 2010 Plan

  50. Specification WG Status • 3.0 errata (and back-rev to 2.2) taking longer than expected • Expect to release by end of month • OCP 3.1 • Performance parameters don’t yet have owner • Likely Sonics with TI support • Transaction IDs unlikely to be included • Memory semantics (memory barriers) work owned by MIPS • Div Bole has produced work plan • Hope to complete work by end Q3/publish early 2011 • OCP 4.0 • No current or planned activity

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