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Simultaneous Sampling ADC Data Acquisition System for the QUIET Experiment

Simultaneous Sampling ADC Data Acquisition System for the QUIET Experiment. Mircea Bogdan, Dorothea Samtleben, Keith Vanderlinde The University of Chicago. Simultaneous Sampling ADC DAQ System for QUIET Block Diagram. One 6U VME Crate; Signals from Preamps;

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Simultaneous Sampling ADC Data Acquisition System for the QUIET Experiment

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  1. Simultaneous Sampling ADC Data Acquisition System for the QUIET Experiment Mircea Bogdan, Dorothea Samtleben, Keith Vanderlinde The University of Chicago Mircea Bogdan, NSS2005 Oct. 23-29, 2005 – Windham El Conquistador Resort, Puerto Rico

  2. Simultaneous Sampling ADC DAQ System for QUIET Block Diagram • One 6U VME Crate; • Signals from Preamps; • 12 ADC Boards: 384 A/D Channels (Up to 640 Channels/Crate); • Local Data processing; • Continuous VME readout; • Control Module for Simultaneous sampling and processing. Mircea Bogdan, NSS2005 Oct. 23-29, 2005 – Windham El Conquistador Resort, Puerto Rico

  3. Simultaneous Sampling ADC DAQ System for QUIET ADC Board – Block Diagram • 32 ADC Channels: - 18-Bit, 800 kSPS; • Separate interface lines; • FPGA: EP1S30F780C6; - Data processing: - 800kHz => 100Hz. - Buffer readout ~ 3Hz. - Experiment Control Mircea Bogdan, NSS2005 Oct. 23-29, 2005 – Windham El Conquistador Resort, Puerto Rico

  4. Simultaneous Sampling ADC DAQ System for QUIET Analog/Digital Conversion Channel • Input = +/- 1V; • Gain = -2; • Offset ~ 0.8V; • One-pole RC low-pass; • AD7674 SAR; • Serial Data Read - 25 ns discontinuous clock. Mircea Bogdan, NSS2005 Oct. 23-29, 2005 – Windham El Conquistador Resort, Puerto Rico

  5. Simultaneous Sampling ADC DAQ System for QUIET Signal Integrity Tests • U_0 – pin AA17 - SDIN; • No termination; • U_0 – pin AA17 - SDIN; • With 33 Ohm series termination; Mircea Bogdan, NSS2005 Oct. 23-29, 2005 – Windham El Conquistador Resort, Puerto Rico

  6. Simultaneous Sampling ADC DAQ System for QUIET Conclusions • 32 Channel, 18 bits, 800 kSPS ADC; • 1 pole input filter – configurable; • Powerful local processing with FPGA; • Low cost, 6U VME, 5V/2A, 3.3V/1A. Built and tested 3 prototypes: • Input noise voltage ~ 15uV RMS; • Channel-to-Channel Skew ~ 5ns. http://quiet.uchicago.edu Mircea Bogdan, NSS2005 Oct. 23-29, 2005 – Windham El Conquistador Resort, Puerto Rico

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