1 / 10

Special Design Report

This report outlines the need for additional PWM channels, the design process, and results achieved. Implementing 2 additional channels is detailed with a focus on locomotion using Altera MAX7032 CPLD. The design includes 3 settings (Forward, Reverse, Stopped) for each channel selection. A 1 MHz clock, Atmel Mega163 microcontroller, and VHDL development are discussed, showcasing successful waveform tests with servos.

sonia-moody
Télécharger la présentation

Special Design Report

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Special Design Report IMDL Summer 2002 Matthew Chernosky July 11, 2002

  2. Overview • Additional hardware Pulse Width Modulation channels • Need for additonal PWM channels • Design • Results

  3. Need for additional channels • Atmel ATMega163 • 3 PWM channels built-in • Motion • Requires 2 channels (left and right) • Golf ball pickup • Needs more than one channel

  4. Design • 2 additional channels to be implemented • Channels used for locomotion • Altera MAX7032 CPLD • Development in VHDL

  5. Design • 3 Settings for each channel • Forward • Reverse • Stopped • A 2-bit wide input bus selects desired setting for each channel • 4 output port pins of uP

  6. Design 1 MHz oscillator Atmel Mega163 Chan A select Altera MAX7032 PWM A Out PWM B Out Chan B select CPLD Microcontroller

  7. Design Reset 15-bit counter Logic FF PWM A 1 MHz clock FF PWM B Chan A select Chan B select CPLD

  8. VHDL ENTITY motor_pwm_580 IS PORT( clk : in STD_LOGIC; PWM_IN_A: in STD_LOGIC_VECTOR(1 downto 0); PWM_IN_B: in STD_LOGIC_VECTOR(1 downto 0); PWM_OUT_A: out STD_LOGIC; PWM_OUT_B: out STD_LOGIC ); END motor_pwm_580;

  9. VHDL cnt: PROCESS (clk) BEGIN IF (clk = '1' and clk'EVENT) THEN if (count < COUNT_MAX) then -- increment counter count <= count + 1; else -- reset counter when COUNT_MAX reached count <= COUNT_RST; end if; END IF; END PROCESS;

  10. Results • Oscilliscope waveform tests • Works with servos 1.75 ms 20 ms

More Related