Layout Guideline for Centralized Clock Solution

1. Layout Guideline for Centralized Clock Solution Clock and Timing Products – HPA/ICP Author & Presenter: Leandro Zaza, Application Engineer

2. Agenda • Centralized clock solution: added values • Transmission Line • Electric Field and Radiation • Signal Routing • Power supply • Centralized clock solution • Appendix A:board component models Centralized clock solution may look like tough, let us make it more doable.

3. Centralized Clock Solution: added values • Advantages: • BOM reduction • Board Space saving • Cost saving: XTAL + capacitor loads • Additional feature (frequency selection, VCXO, …) • Possibility to reach 0ppm frequency error without any external component • Drawback: • Awareness of board layout techniques needed

4. Transmission Line When must we treat a trace like a transmission line? If the trace length is bigger than: L = trace length tR = rise time (10% to 90%) tPR = signal propagation rate. For FR4, 150ps/in < tPR < 175ps/in tR can be approximated as Under the below condition the trace needs to be considered and analyzed as transmission line

5. Transmission Line How to treat a transmission line? R = series resistance of the conductor per unit length L = series inductance of the conductor per unit length C= capacitance due to dielectric layer per unit length G= admittance due to dielectric layer per unit length Propagation Equation Characteristic Impedance Lossless trace

6. Transmission Line: current path A conductor that carries current requires an opposite mirror current to return through some part of the system. This return current path will be the least resistance and least inductance. The return current density is function of the distance from the edge of the signal trace (D) @ D/h = 5 current density = 4% of the maximum that occurs right beneath the trace @ D/h = 10 current density = 1% of the maximum that occurs right beneath the trace Adjacent traces must be place not too close to each other in order to avoid crosstalk due to return currents interaction

7. Transmission Line: current path For differential signaling formats (LVDS, LVPECL, …) the return path is provided by a second signal trace The current flowing in our trace of the pair, will flow back through the other trace, completing the current loop Real signal will have some common mode current that will “capacitively” coupled to ground lane and return to the driver through the least resistive path. Traces of the differential pair must be place close to each other in order to avoid big antenna loop

8. Transmission Line: design Differential Microstrip edge coupling Differential Stripline edge coupling Broadside Stripline width coupling

9. Transmission Line: reflection Reflection coefficient gives the ratio between the reflected voltage amplitude and the incident voltage amplitude at the receiver. Rs A B Zo rA rB RL Vs Rs: clock source output impedance RL: termination Z0: transmission line characteristic impedance Ideally ρ must be 0 meaning RL=Z0. Any discontinuity in the impedance value during the signal propagation path will generate reflections.

10. Transmission Line: reflection Propagation Delay: 550ps

11. EMI origin The Electric Field around a conductor is proportional to the voltage or current which flows. Single Ended  maximum radiation (TEM) Balanced Differential Ended  coupled electric fields are tied up and cannot escape Unbalanced Differential Ended  excess in the fringing field Single Ended Balanced Differential Unbalanced Differential

12. EMI origin Emissions due non-idealities

13. EMI reduction: design Field distribution in transmission line How to further reduce? Shield traces to GND on both sides

14. EMI reduction: design Differential signal Minimize the imbalances between the conductors of each pair Close coupling between the conductors of each pair (less antenna loop area) Reduce the noise coupled onto the conductors  it will be transferred as common mode noise which will be rejected by the receiver.

15. EMI reduction: design For single ended signal : Slew Rate Control Spread Spectrum Clock (SSC)

16. CDCE706/906Six Output Flexible Clock Synthesizer Features Benefits • Highly integrated solution reduces board space • Enables low EMI designs via SSC and Slew Rate Control. • Reduces Cost by consolidating crystals and clock devices into one package • Can be operated without host control via EEPROM startup • Customer programmable default settings • Universal Input (Single Ended or Crystal) • Three Low Noise Fractional Synthesizers • Integrated PLL, VCO, Loop Filter • Period Jitter 60 ps typical • SSC clocking support (one clock domain) • Six Outputs • Frequencies up to 300 MHz • Programmable Slew Rate Control • Innovative crosspoint/divider array • Host Interface – SMBus • On Chip EEPROM Applications • Consumer Clocking • Embedded Systems • Computing TI Confidential – NDA Restrictions

17. Samples NOW CDCUN1208LPUltra Low Power Universal Fan-out Buffer Benefits Features • Low Additive Jitter (< 300 fs RMS< 10k-20M, 100 MHz) • Configurable I/O • HCSL, LVDS, or LVCMOS • LVCMOS can be 1,8, 2.5, or 3.3V (mix and match) • Internal Termination • 8 Output Version (up to 400 MHz) • Low Power and Power Management Modes • Active: 10 mA/output @ 100 MHz, LVDS Mode • Standby: < 0.8 mA • Edge Rate Control • Slow, Medium, and Fast Edge Rate Setting • Different edge rates for each I/O type • Configuration via pins or serial interface • QFN32 (8 Output) • Low Jitter improves communications reliability and jitter budget margin. • Low Power Consumption and Power Management Features suitable for portable systems. • Low EMIEmissions via Edge Rate Control • Configurable I/O, Small Package, and Internal Termination conserves board space, eliminates external components, and improves reliability and performance. Applications • Systems • Networking, Medical Imaging, Communications Infrastructure, Portable Systems • Applications • Clock tree fan out, clock level translation, buffer consolidation.

18. CDCE9xxFlexible Clock Synthesizer Family Features Benefits • Highly integrated solution reduces board space • Enables low EMI designs via SSC • Reduces Cost by consolidating crystals and clock devices into one package • Can be operated without host control via EEPROM startup • Customer programmable default settings • Flexible Input (Single Ended or Crystal) • One/Two/Three/Four Low Noise Fractional Synthesizers • Integrated PLL, VCO, Loop Filter • Period Jitter 60 ps typical • SSC clocking support • Three/Five/Seven/Nine Single Ended Outputs • Frequencies up to 300 MHz • Flexible Supply Options • 2.5V, 3.3V (CDCE9xx) • 1.8V (CDCEL9xx) • Host Interface – SMBus • On Chip EEPROM Applications • Consumer Clocking • Embedded Systems • Computer Peripherals TI Confidential – NDA Restrictions

19. CDCS501/503NEW - EMI ExpertClock Driver with Optional Spread Spectrum Clocking (SSC) • Wide Input/Output freq. range • 40 - 115 MHz for 501 • 8 – 32MHz Input/8-108MHz Output for 503 • Selectable Spread-Spectrum Modulation of ±0.0%, ±0.5%,±1.0%, and ±2.0% • Selectable frequency multiplication rates of 1x and 4x (CDCS503 only) • 8 pin TSSOP package • Operation condition: Single 3.3V power supply, wide temperature range -40 , 85 • Saves BOM: single device covers multiple designs • Reduce EMI thru selectable amount of SSC modulation up to 10dB • Saves component for higher frequency XO • Small board space • Simple power supply scheme; applicable to wider applications with better reliability • General purpose clock driver • with EMI reduction capability: • Audio/Video entertainment • Flat Panel TV; Set-top Boxes; • Blue-Ray DVDR • Printers; PCs • Communications access point/gateway/networking card • Industrial TI Confidential – NDA Restrictions

20. CDCS502NEW - EMI ExpertXtal-In Clock Generator with Optional Spread Spectrum Clocking (SSC) • Replacing more costly crystal oscillators • Wider output frequency range enables one device across multiple designs • Reduce EMI thru selectable amount of SSC modulation up to 10dB • Low board space consumption • Simple power supply scheme; Applicable to wider applications with improved reliability • Crystal input from 8MHz to 32MHz • Selectable multiplier rates of 1x and 4x so that generate output frequency from 8MHz to 110MHz • Selectable Spread-Spectrum Modulation of ±0.5%, ±1.0%, and ±2.0% • 8 pin TSSOP package • Single 3.3V power supply, wide temperature range -40 , 85 • XO replacement with EMI reduction need: • Digital Audio/Video Entertainment • Flat Panel TV; Set-top Boxes; Blu-Ray DVDR • PCs, Printers • Communications access point/gateway/networking card • Industrial TI Confidential – NDA Restrictions

21. Coupling Zones Signal Routing: coupling and crosstalk • To reduce coupling, we should: • Increase Isolation between aggressor and victim • Isolate the Power supplies • Make sure the ground is low impedance to reduce ground bounce • Trace spacing: • Single Ended signals return current density drops to 4% when D/H =5 and drops to 1% when D/H = 10. • Differential signals • distance between two pairs should be >2S, • distance between a pair and SE signal trace >3S or even better to different plane • guard ground trace or ground fill distance >2S

22. Signal routing: minimizing the skew Minimize the propagation time difference between the two signals of a differential pair. A mismatch generates common mode noise that will be emitted as radiation. The propagation velocity on a board is given by: c = 0.2998 mm/ps speed velocity εr = dielectric constant ( for FR-4 is 4.2) The reciprocal will give us the propagation time for 1mm board trace. For FR-4 case this is 6.84ps Match the lengths of a pair within 1/20 of the signal rise time.

23. Signal routing: minimizing the skew Loss Tangent quantifies the dissipation of the electromagnetic energy

24. Signal routing

25. Power Supply When a load is suddenly applied to a voltage source, the circuit tries to suddenly increase its current, but the inductance in the power supply line acts to oppose that increase. It opposes it by lowering the voltage of the power line supplies. The job of a decoupling or bypass cap, is to supply short bursts of current when the IC needs it. Caps act as battery Decoupling (bypass) capacitors between the power supply and ground - lowers the distributed impedance of a system - reduces the system noise - lowers EMI The values of the decoupling cap should be chosen to provide the lowest impedance at the frequencies of interest.

26. Power Supply Ensure low ac impedance to reduce noise and to store energy To reach low impedance over a wide frequency range, several capacitors must be used F

27. Power Supply • DO NOT have vias between bypass caps and active device – Visualize the high frequency current flow !!! • Ensure Bypass caps are on same layer as active component for best results. • Route vias into the bypass caps and then into the active component. • The more vias the better. • The wider the traces the better. • The closer the better (<0.5cm, <0.2”) • Two or Multi-Layer Ceramic surface mounting capacitors in parallel should be placed at each VCC pin Poor Bypassing Good Bypassing

28. Power Supply • Reasons to not split the ground plane: • Strong chance for error in making the split. • Could cause a large inductive loop which gives rise to noise. • Fact: With proper decoupling and grounding, many single GND planes perform as good as split ground planes.

29. Power Supply If Ground Split is needed: do not let one ground plane pass another ground plane to get connected to the common ground Poor Good

30. Centralized clock solution Enormous reflections at the branches and the different trace length to the devices. Because of the delay, it is possible that the system cannot function properly Star connection is a good solution to minimize the delay Same trace length to minimize the skew Reduced reflections but still because of delay, it can be possible that the data, sent from device A to device B, is out of date when the clock signal arrives at device B Daisy chain: not recommended

31. Centralized clock solution Single ended traces should be placed not closer than 5h or even farther Minimize parallel runs Uses shield traces Straight clock traces is best. If direction change unavoidable:

32. Centralized clock solution Do not route clock traces through different layers Traces for differential signaling should be closely coupled and keep constant In order to fine tune Zo, it is better to adjust trace width (W) rather than adjusting spacing (S). Spacing should be kept as small as possible to reduce the antenna loop.

33. Reference • “Clock Conditioner Owner’s manual”: Winter 2006 – First Edition “TI Proprietary Information - Strictly Private” or similar placed here if applicable

34. Appendix A

35. Capacitor Models Best Model Ideal Model Better Model

36. Attention to Data sheet! Pay attention to types of Cap

37. Vref settling issue • Problem statement: • VREF is taking 1s to settle during power up or waking up from sleep. This is causing DCXO frequency not able to settle to +/-0.1ppm within 5ms. • Root causes for the issue: • There’s a 20mV dip of VREF measured in the lab after the quick charge circuit is turned off. Due to the large time constant (~200ms) of the RC filter at VREF output, it takes long to settle to the final value.

38. Vref settling issue 100ms 300ms 200ms

39. Inductor Models Best Model Better Model Ideal Model

40. Attention to Data sheet! Example on a DC-DC converter

41. Resistor Models Best Model • Using SMT resistors minimizes lead inductance to the point that PCB traces are the limiting factor • SMT packages also minimize the capacitance between the leads such that this parasitic is usually insignificant • Note that resistor packs CAN have significant lead inductance and resistor-to-resistor capacitance, so choose wisely based on the application • Resistors will have temperature coefficients, 200PPM is common, but higher precision is available • AVOID Wire-wound resistors and leaded resistors for high speed applications due to their large inductance Ideal Model Better Model