Créer une présentation
Télécharger la présentation

Télécharger la présentation
## Digital Testing: Sequential Circuits

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -

**Digital Testing: Sequential Circuits**Based on text by S. Mourad "Priciples of Electronic Systems"**Outline**• Issues in testing sequential circuits • Types of Tests • Functional • Deterministic • Checking experiment • Iterative array**Importance of Sequential Circuits**• Most circuits are sequential • The outputs depends on the input and the internal states • Must drive the circuit first in a know state prior to applying the patterns that sensitize the faults to the outputs: • Use global reset or • a synchronizing sequence • Timing is an important factor • Static and essential hazard**Types of Tests**• Exhaustive: 2i+s McCluskey 1981 • Pseudorandom Wunderlich 1989 • Not effective because it is not sufficient to apply the patterns, they should be done in the appropriate sequence • Checking experiment • Fault oriented, adaptation of combinational test • Check literature for more recent algorithms**Checking Experiment**• Synchronizing sequence SS: place the FSM in a known state • Homing sequence HS: places the FSM in a known state that is identifiable by the output sequence • Distinguishing sequence DS: produces an output sequence that defines uniquely the initial state at which the sequence was applied • Transition sequence TS: indicates the transition form one state to any other**State Table Verification for Sequential Circuit**Moore Theorem: For any reduced strongly connected (no equivalent states & any state reachable from another state) n-state sequential machine M, there is an input-output sequence pair that can be generated by M but can not be generated by any other sequential machine with n or fewer states This sequence is called checking sequence**State Table Verification for Sequential Circuit**Given the state table of a sequential machine, find an input /output sequence pair (X,Z) such that the response to X will be Z iff machine is fault free. Then (X,Z) is called checking sequence and test is called checking experiment**State Table Verification for Sequential Circuit**Homing sequence is x=101 since the final state can be uniquely defined: initial state/output final state state A D,0 C,0 C,1 B B,1 D,0 A,0 C C,1 B,0 B,1 D A,0 C,1 C,1 Example : State table present input state x=0 x=1 A C,1 D,0 B D,0 B,1 C B,0 C,1 D C,0 A,0**State Table Verification for Sequential Circuit**Definition : Distinguishing sequence is such an input sequence X that will produce different output sequence for each initial state (so the initial state can be distinguished) Every distinguishing sequence is a homing sequence but not opposite**State Table Verification for Sequential Circuit**• Uncertainty is a collection of sates which is known to contain the present state. • Asuccessor tree is a structure which displays successor uncertainties for all input sequences xi • A collection of uncertainties is an uncertainty vector • An uncertainty vector whose components contain a single state, each is trivial • A vector whose components contain single states or identical repeated states is homogeneous**State table verification for sequential circuit**Algorithm to generate homing sequence: Homing sequence - path from root to trivial or homogenous vector. Homing tree is a successor tree in which a node becomes terminal if : 1. Non-homogenous components in an uncertainty vector are the same as on the previous level 2. Uncertainty vector is trivial or homogeneous**State table**present input state x=0 x=1 A B,0 D,0 B A,0 B,0 C D,1 A,0 D D,1 C,0 State Table Verification for Sequential Circuit Example : Consider FSM**Example :**(ABCD) (AB(DD) (ABCD) (AB)(DD) (BD)(CC) (A)(D)(DD) (BC)(AA) (A)(D)(BB) (AB)(DD) 1 0 0 1 State table present input state x=0 x=1 A B,0 D,0 B A,0 B,0 C D,1 A,0 D D,1 C,0 0 1 same 1 0 homing Homing Sequence**Algorithm to generate a distinguishing sequence**Distinguishing sequence - path from root to trivial vector. A distinguishing tree is a successor tree in which a node becomes terminal if 1. Non-homogenous components in an uncertainty vector are the same as on the previous level 2. Uncertainty vector contains a homogeneous non-trivial component (does not have to be a homogeneous vector) 3. Uncertainty vector is trivial**present input**state x=0 x=1 A A,0 C,1 B B,0 D,1 C A,1 C,0 D D,0 B,0 State table verification for sequential circuit Example : Consider the following state table**present input**state x=0 x=1 A A,0 C,1 B B,0 D,1 C A,1 C,0 D D,0 B,0 Asuccessor tree Finding distinguishing sequence (ABCD) (ABD)(A) (BC)(CD) (A)(ABD) (B)(CD)(C) (B)(A)(A)(D) (D)(C)(BC) (B)(A)(D)(A) (D)(CB)(C) (D)(A)(B)(A) (B)(C)(D)(C) (D)(A)(B)(A) (B)(C)(D)(C) 1 0 0 0 1 1 0 1 0 1 1 0**State table**present input state x=0 x=1 A B,0 D,0 B A,0 B,0 C D,1 A,0 D D,1 C,0 (ABCD) (AB)(DD) (ABCD) 0 1 State table verification for sequential circuit Example : Consider FSM Homogeneous component No distinguishing sequence**State table**present input state x=0 x=1 A A,0 C,1 B B,0 D,1 C A,1 C,0 D D,0 B,0 Input sequence X = 1,0 initial input state x=1 x=0 A C,1 A,1 B D,1 D,0 C C,0 A,1 D B,0 B,0 so X=1,0 distinguishing Distinguishing Sequence Example : Consider FSM, different output vectors for different initial state**B**B D 0 1 0 1 D B Transfer Sequence Transfer sequence - takes machine from one state to another Example : Consider previous FSM (no transfer sequence) Not strongly connected FSM**0/1**B A State table present input state x=0 x=1 A B,1 C,0 B A,0 D,1 C B,0 A,0 D C,1 A,1 0/0 B 0/0 1/1 1 1/0 0 1/1 1/0 D A C 1 D 0 0 1 0/1 A B C C Transfer Tree Example : Consider the following FSM we get the transfer tree To get from B to C we can select x = 1,0**State table verification for sequential circuit**Synchronizing sequence takes machine to the specific final state regardless of the output or initial state - does not always exists Example : Algorithm to generate synchronizing sequence : Consider the previous machine with synchronizing sequence x= 1,1,0**(ABCD)**(ABC) (ACD) (AB) (ACD) (BC) (AC) (AB) (CD) (AB) (AD) (B) (AC) Synchronizing Sequence Example : 1 0 0 1 1 0 0 0 0 1 1 1**Designing checking experiments**Machine must be strongly connected & diagnosable ( i.e. have a distinguishing sequence) 1. Initialization (take it to a fixed state[s]) a) Apply homing sequence & identify the current state b) Transfer current state to S 2. Identification (make machine to visit each state and display response) 3. Transition verification (make every state transition result checked by distinguishing sequence)**(ABCD)**(BC)(AB) (AC)(AD) (AB)(A)(B) (A)(C)(D)(D) State table present input state x=0 x=1 A B,1 C,0 B A,0 D,1 C B,0 A,0 D C,1 A,1 1 0 1 0 Designing checking experiments Example : Consider FSM 1.Initialization: Successor tree Found distinguishing sequence x = 0,1 (so it is a homing sequence as well) and the current state is determined**Initial Input final**states 0 1 states A B,1 D,1 D B A,0 C,0 C C B,0 D,1 D D C,1 A,0 A State table present input state x=0 x=1 A B,1 C,0 B A,0 D,1 C B,0 A,0 D C,1 A,1 Designing checking experiments Example (Initialization cont.) : After applying distinguishing sequence 0 1**Initial Input final**states 0 1 states A B,1 D,1 D B A,0 C,0 C C B,0 D,1 D D C,1 A,0 A present input state x=0 x=1 A B,1 C,0 B A,0 D,1 C B,0 A,0 D C,1 A,1 time 1 2 3 4 5 6 7 8 9 10 11 input 0 1 0 1 0 0 10 10 1 state A D A B C D A output 1 1 1 0 1 0 0 0 1 1 0 Designing checking experiments 2. Identification: Visit each state and analyze the results**State table**present input state x=0 x=1 A B,1 C,0 B A,0 D,1 C B,0 A,0 D C,1 A,1 time 1 2 3 input 0 0 1 state A B C output 1 0 0 3. Transition verification: Check transition from A to B with input 0, then apply distinguishing sequence 01 to identify the initial state before transition Designing checking experiments**Designing checking experiments**Example : Check transition from C to B with input 0 and from C to A with input 1, and so on. The entire checking test time 1 2 3 4 5 6 7 8 9 10 11 input 0 0 1 0 0 1 1 0 1 0 0 state A B C B C A D C output 1 0 0 0 0 0 0 1 1 1 0**Designing checking experiments**time 12 13 14 15 16 17 18 19 20 21 input 1 1 0 1 0 1 0 0 0 1 state D A D B A output 1 1 1 1 1 0 1 0 1 1 time 22 23 24 25 26 27 28 29 30 31 input 1 1 0 1 0 1 0 1 0 1 state D A C D B D A output 1 0 0 1 1 0 1 1 1 0**DFT for sequential circuits**Critical testability problems 1. Noninitializable design - change design to have a synchronizing sequence 2. Effects of component delays - check for hazard & races in simulation 3. Nondetected logic redundant faults -do not use logic redundancy 4. Existence of illegal states - avoid add transition to normal states 5. Oscillating circuit - add extra logic to control oscillations**DFT for sequential circuits**Checking experiments can not be applied for FSM without a distinguishing sequence Modification procedure for such FSM: I. Construct testing table upper part contains states & input/output pairs lower part contains products of present & next states with the rule that (state)*(-) = (-) II. Construct testing graph**present input/output**state 0/0 0/1 1/0 1/1 A A - B - B A - C - C - AD - D - AA - AB AA - BC - AC - - BD - AD - - AB - BC - - CD - BD - - AC - CD - AAAD - DFT for sequential circuits Testing table for machine Example: state table present input state x=0 x=1 A A,0 B,0 B A,0 C,0 C A,1 D,0 D A,1 A,0**DFT for sequential circuits**II . Construct testing graph An edge Xp/Zp exists directed from present state SiSj to next states SkSl if SkSl (k l) is present in row SiSj under Xp/Zp Example: for our machine we have: 1/0 1/0 AB BC AC 1/0 1/0 1/0 1/0 BD AD CD**DFT for sequential circuits**A machine is definitely diagnosable if its testing graph has no loops and there are no repeated states (i.e. no circled states in testing table) – so the example machine is not definitely diagnosable In order to make machine definitely diagnosable additional outputs (up to k = log (# states ) ) are required**Testing graph**1/01 1/00 present input state x=0 x=1 A A,00 B,01 B A,01 C,00 C A,10 D,00 D A,11 A,01 AD BA BC CD DFT for sequential circuits Example: (with added output) After machine is modified to have distinguishing sequence apply checking experiment procedure to test it.**Sequential Circuit Testing**1. Cut the few of the feedback wires to make the circuit acyclic 2. Each feedback wire is a pseudo input and a pseudo output 3. Consider different time frames decided by the clock and the inputs values 4. Use D-algorithm or any other to detect the faults 5. Start with the final time frame at which the fault is observed and trace backward to an earlier frame until the signal is justified 6. The PI cannot be assigned any values x I = 7. Repeat 5 until all signal are justified, if there is a conflict, trackback and select another justification path**k**m Z I Sequential n Circuit (a) Feedback Circuit. m k I Z Copy 1 Copy 2 Copy j n n n SI SO SO SI Z (b) Time Frame Based Model. Sequential Circuit Model**0**0 2 2 10 10 1 5 5 3 3 1 1 1 6 6 1 D 0 0 SI5 12 12 9 9 0 D D' 4 4 D' 1 0 1 14 D' 13 13 14 1 1 1 7 7 0 D' 0 0 1 8 8 11 11 SI13 SI13 0 Frame Frame 1 2 Time Frames**D'**D D d D' X3 SET 3 D Q output 1 4 F1 f Q CLR SET X2 e D Q F2 D' 5 Q CLR a b c 2 SET D Q X1 s-a-1 F3 Q CLR Another Example**PI3**D' D X3 D' D Z SET 3 D Q 1 4 4 X3 SET 3 D Q 1 4 F1 Z 4 F1 1 Q Q CLR CLR X2=1 1 1 SET D Q SET D Q F2 X2=1 F2 D P03 5 Q 5 Q CLR P03 CLR c SA1 b X1=1 2 SET D Q 2 SET D Q D' F3 D' F3 Q Q CLR CLR Time Frames Example 2**a2**b2 a1 b1 a0 b0 G2 G1 G0 P2 P1 P0 C1 C0 Cin C2 S2 S1 S0 EXAMPLE 1 – TEST for p STUCK- AT - 0 Provoke Fault on p1: a1=0, b1=1, Propagate Fault to S2: C0=1, a2=0, b2=0 Justify C0=1: a0=1, b0=1, Cin=x**1**1 0 1 1 1 0 0 Second input to e First input to h Don’t care**1**0 1 1