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Fundamentals of Digital System Design

Fundamentals of Digital System Design. Pradondet Nilagupta Lecture 8: Synchronous Sequential Circuits Chapter 8. Synchronous Sequential Circuits. Sequential circuits – outputs depend on past behavior as well as present inputs. Synchronous circuits – use a clock signal to sequence behavior.

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Fundamentals of Digital System Design

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  1. Fundamentals of Digital System Design Pradondet Nilagupta Lecture 8: Synchronous Sequential Circuits Chapter 8

  2. Synchronous Sequential Circuits • Sequential circuits – outputs depend on past behavior as well as present inputs. • Synchronous circuits – use a clock signal to sequence behavior. • Asynchronous circuits – no clock signal is used (see Chapter 9).

  3. W Combinational Combinational Z Flip-flops circuit circuit Q Clock Figure 8.1 The general form of a sequential circuit

  4. Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 0 1 0 0 1 1 0 A Simple Example • Circuit has one input, w, and one output, z. • Changes occur on positive clock edge. • z is 1 if w is 1 during last two clock cycles. Figure 8.2 Sequences of input and output signals

  5. Reset w = 1 ¤ ¤ A z = 0 B z = 0 w = 0 w = 0 w = 1 w = 0 ¤ C z = 1 w = 1 Figure 8.3 State diagram of a simple sequential circuit

  6. Next state Present Output z state w = 0 w = 1 A A B 0 B A C 0 C A C 1 Figure 8.4 State table

  7. Y y 1 1 w Combinational Combinational z circuit circuit Y y 2 2 Clock Figure 8.5 A general sequential circuit

  8. Next state Present Output w = 0 w = 1 state z y y Y Y Y Y 2 1 2 1 2 1 00 00 01 A 0 01 00 10 B 0 10 00 10 C 1 11 dd dd d Figure 8.6 A State-assigned table

  9. y y 2 1 Ignoring don't cares Using don't cares 00 01 11 10 w 0 0 0 d 0 Y = wy y Y = wy y 1 2 1 2 1 1 1 1 0 d 0 y y 2 1 w 00 01 11 10 0 0 0 d 0 Y = wy y + wy y Y = wy + wy 2 1 2 1 2 2 1 2 1 0 1 d 1 ( ) = w y + y 1 2 y 1 y 2 0 1 0 0 0 z = y y z = y 1 2 2 1 1 d Figure 8.7 Derivation of logic expressions

  10. Figure 8.8 Sequential circuit

  11. t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 1 Clock 0 1 w 0 1 y 1 0 1 y 2 0 1 z 0 Figure 8.9 Timing diagram

  12. Summary of Design Steps • Obtain specification of the desired circuit. • Create a state diagram from specification. • Create a state table from state diagram. • Perform state minimization. • Perform state assignment. • Derive the next-state logic expressions. • Implement circuit described by logic.

  13. Data Extern Bus Clock R 1 R 2 Rk R 1 R 1 R 2 R 2 Rk Rk in out in out in out Control circuit Function Figure 7.56 A digital system with k registers

  14. , , , R 2 R 3 R 1 R 2 R 3 R 1 out in out in out in w Q Q Q D D D Clock Q Q Q Reset Figure 7.58 A shift-register control circuit

  15. R 1 out R 1 in w R 2 out Control R 2 circuit in R 3 out Clock R 3 in Done Figure 8.10 Signals needed in Example 8.1

  16. w = 0 ¤ A No Reset transfer w = 1 ¤ , B R 2 = 1 R 3 = 1 out in w = 0 w = 1 w = 0 w = 1 ¤ , C R 1 = 1 R 2 = 1 out in w = 0 w = 1 ¤ , , D R 3 = 1 R 1 = 1 Done = 1 out in Figure 8.11 State diagram

  17. Next state Outputs Present state w = 0 w = 1 A A B 0 0 0 0 0 0 0 B C C 0 0 1 0 0 1 0 C D D 1 0 0 1 0 0 0 D A A 0 1 0 0 1 0 1 Figure 8.12 State table

  18. Figure 8.13 State-assigned table

  19. Figure 8.14 Derivation of next-state expressions

  20. Figure 8.15 Sequential circuit

  21. Next state Present Output state w = 0 w = 1 z y y Y Y Y Y 2 1 2 1 2 1 A 00 00 01 0 B 01 00 11 0 C 11 00 11 1 10 dd dd d Figure 8.16 Improved state assignment 1

  22. Y y 2 2 z Q D Q Y y 1 1 w Q D Q Clock Resetn Figure 8.17 Final circuit for the improved state assignment

  23. Figure 8.18 Improved state assignment

  24. y y 2 1 w 00 01 11 10 0 1 Y = wy + y y 2 2 1 1 1 1 1 y y 2 1 w 00 01 11 10 0 1 1 Y = y 2 1 1 1 1 Figure 8.19 Derivation of next-state expressions

  25. Nextstate Present Output state w = 0 w = 1 z y y y Y Y Y Y Y Y 3 2 1 3 2 1 3 2 1 A 001 001 010 0 B 010 001 100 0 C 100 001 100 1 Figure 8.20 One-hot state assignment 1

  26. Figure 8.21 One-hot state assignment

  27. Clock cycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 Mealy State Model • Moore machines – output is determined only be present state. • Mealy machines – output depends on both present state and input values. Figure 8.22 Sequences of input and output signals 1

  28. Reset ¤ w = 1 z = 0 ¤ ¤ w = 0 z = 0 w = 1 z = 1 A B ¤ w = 0 z = 0 z Next state Output Present state w = 0 w = 1 w = 0 w = 1 A A B 0 0 B A B 0 1 Figure 8.23 State diagram

  29. Next state Output Present z Next state Output state Present w = 0 w = 1 w = 0 w = 1 state w = 0 w = 1 w = 0 w = 1 y Y Y z z A A B 0 0 A 0 0 1 0 0 B A B 0 1 B 1 0 1 0 1 Figure 8.24 State table

  30. z w Q D y Clock Q Resetn (a) Circuit t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 1 Clock 0 1 w 0 1 y 0 1 z 0 (b) Timing diagram Figure 8.26 FSM implementation

  31. Figure 8.27 FSM implementation

  32. w = 0 Reset A ¤ , w R R = 1 2 = 1 3 = 1 out in B w = 0 , R R 1 = 1 2 = 1 out in w = 1 C w = 0 , , R R Done 3 = 1 1 = 1 = 1 out in w = 1 Figure 8.28 State diagram for Example 8.4

  33. , , , R 2 R 3 R 1 R 2 R 3 R 1 out in out in out in Reset w P Q Q Q D D D Q Q Q Clock Figure 7.59 A modified control circuit

  34. Design of FSMs using CAD tools • Could design using manual techniques then use schematic capture or structural VHDL. • Instead should enter state table via a state diagram editor or behavioral VHDL.

  35. USE ieee.std_logic_1164.all ; ENTITY simple IS PORT ( Clock, Resetn, w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END simple ; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN con’t ... Figure 8.29a VHDL code for a simple FSM

  36. CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ; END IF ; END PROCESS ; z <= '1' WHEN y = C ELSE '0' ; END Behavior ; Figure 8.29b VHDL code for a simple FSM (con’t)

  37. Interconnection wires Resetn Clock w PAL-like block 1 1 0 y 1 D Q 1 1 0 y 2 D Q 0 1 0 z D Q (Other macrocells are not shown) Figure 8.30 Implementation of an FSM in a CPLD

  38. Figure 8.31 An FSM circuit in a small CPLD

  39. (a) Timing simulation results (b) Magnified simulation results, showing timing details Figure 8.32 Simulation results

  40. (ENTITY declaration not shown) ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; Figure 8.33a Alternative style of code for an FSM

  41. WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ; PROCESS (Clock, Resetn) BEGIN IF Resetn = '0' THEN y_present <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ; z <= '1' WHEN y_present = C ELSE '0' ; END Behavior ; Figure 8.33b Alternative style of code for an FSM (con’t)

  42. (ENTITY declaration not shown) ARCHITECTURE Behavior OF simple IS TYPE State_TYPE IS (A, B, C) ; ATTRIBUTE ENUM_ENCODING : STRING ; ATTRIBUTE ENUM_ENCODING OF State_type : TYPE IS "00 01 11" ; SIGNAL y_present, y_next : State_type ; BEGIN con’t ... Figure 8.34 A user-defined attribute for manual state assignment

  43. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY simple IS PORT ( Clock, Resetn, w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END simple ; ARCHITECTURE Behavior OF simple IS SIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNTO 0); CONSTANT A : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00" ; CONSTANT B : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01" ; CONSTANT C : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11" ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; … con’t Figure 8.35a Using constants for manual state assignment

  44. WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; WHEN OTHERS => y_next <= A ; END CASE ; END PROCESS ; PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN y_present <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ; z <= '1' WHEN y_present = C ELSE '0' ; END Behavior ; Figure 8.35b Using constants for manual state assignment (cont’)

  45. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mealy IS PORT ( Clock, Resetn, w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END mealy ; ARCHITECTURE Behavior OF mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; … con’t Figure 8.36 VHDL code for a Mealy machine

  46. WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ; END IF ; END PROCESS ; PROCESS ( y, w ) BEGIN CASE y IS WHEN A => z <= '0' ; WHEN B => z <= w ; END CASE ; END PROCESS ; END Behavior ; Figure 8.36b VHDL code for a Mealy machine (con’t)

  47. Figure 8.37 Simulation results for the Mealy machine

  48. Figure 8.38 Potential problem with asynchronous inputs to a Mealy FSM

  49. A a Shift register s Adder Shift register FSM Shift register b Sum A B = + B Clock Figure 8.39 Block diagram of a serial adder

  50. Figure 8.40 State diagram for the serial adder

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