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Upgrade of LHC Detectors: Summary for ATLAS

Upgrade of LHC Detectors: Summary for ATLAS. Presentation Overview. Motivations and expected schedule Organisation of upgrade activities Main changes expected Upgrade of Inner Detector for SLHC Developments in Electronics for the Tracker Conclusions. Super LHC.

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Upgrade of LHC Detectors: Summary for ATLAS

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  1. Upgrade of LHC Detectors: Summary for ATLAS Philippe Farthouat, CERN

  2. Presentation Overview • Motivations and expected schedule • Organisation of upgrade activities • Main changes expected • Upgrade of Inner Detector for SLHC • Developments in Electronics for the Tracker • Conclusions

  3. Super LHC Improve the luminosity by a factor 10 : 1034 1035 cm-2 s-1 • Physics motivation • Increased physics reach in most typical LHC physics channels • It is not clear today if these improvements are absolutely crucial for new physics, or rather if they represent (gradually) better measurements and better exploitation of the LHC energy domain • However, in either case upgrading the LHC seems very attractive and an obvious next step to plan for • Pragmatic view • The luminosity will increase as function of time at LHC, we will need to upgrade the detectors to take advantage of this • Some parts of the detector systems might have performance problems or operational problems, and will therefore require interventions and improvements faster than foreseen today • An impressive expertise about the construction has been accumulated and it is known today how to improve the detectors

  4. Driven by this plot, but also by lifetime of IR quads 700 fb-1 LHC Upgrade:Machine / Detector Interface • The most relevant parameters for the detectors • BCO interval: 25ns, 15ns, 12.5ns, 10ns (or 75ns) • Forward area/beam pipe : Would like to move the closest machine element towards the IP • Timescales : assume 2014±2 years • Increased radiation levels (and resulting activation) : Need to improve shielding, moderators, access procedures, and safety in general – important constraint for any change considered

  5. Starting points SLHC discussions in ATLAS • Assumed luminosity L = 1035 cm-2 s-1 • Timescale • upgrade to be finished in 2015 • Less appealing aspects need to be taken into account from the very beginning • Constraints from space for services, power consumption, installation scenarios, … • Proper design of services • Anti-magnetic • Low mass • Radiation hard • Reliable • We need to know more precisely the radiation background at the present LHC (especially for the muon system) • Even though safety factors have been applied • X5 for the muon spectrometer • Much more for electronics

  6. Production Pre-series Experience from the past:Path from TDR to Completion • Conclusion from this: we should have TDR in 2008 • Later would shift the completion date away from 2015 • But 2008 is too early for getting sufficient data from LHC • TDR will be later than 2008 • The ID upgrade has to be done faster than the present ID was done • Limited time for fundamental detector R&D Ref: talk of Tyndel at Genova tracker upgrade workshop http://agenda.cern.ch/fullAgenda.php?ida=a053875

  7. Presentation Overview • Motivations and expected schedule • Organisation of upgrade activities • Main changes expected • Upgrade of Inner Detector for SLHC • Developments in Electronics for the Tracker • Conclusions

  8. High Luminosity Steering Group (HLSG) Since 2 years Activities on SLHC upgrade growing within ATLAS Addressed on ATLAS overview weeks since Sept 2004 Upgrade workshop (CERN) on February 13, 14, 2005 Tracker upgrade workshop (Genova) on 18 –20 July, 2005 Upgrade organisation: Project Office project office leader  deputy steering group chairperson project office engineer (sub)system project office engineers Project Office should technically guide the upgrade activities Conceptual design and R&D Prototyping Pre-series and construction Installation and commissioning Organisational structure Ref: https://edms.cern.ch/file/690177/1/Upgrade_Org_PO.doc

  9. Established lightweight procedure for R&D Does the proposal fit into the activity matrix? Scientific merit? Useful for ATLAS? Circulation to collaboration board More groups joining? Second discussion in HLSG Sufficient resources? Decision about recommendation by HLSG Several proposals issued so far Radiation test of opto devices Development of the stave model for silicon modules Read-out ASIC for the silicon tracker Dedicated high intensity test beam underway for 2006 and 2007 ATLAS would welcome joint R&D activities with other experiments (CMS) Optoelectronic RO including radiation-hardness qualification 130 nm or lower processes Coordination of R&D activities • Way of selecting solutions after R&D to be defined • Schedule must be defined clearly enough so that date of decision is known and agreed upon

  10. Presentation Overview • Motivations and expected schedule • Organisation of upgrade activities • Main changes expected • Upgrade of Inner Detector for SLHC • Developments in Electronics for the Tracker • Conclusions

  11. Areas with significant changes Complete Inner detector Parts of muon system LAr endcap calorimeter

  12. BCOs considered 10, 12.5,15, 25 and 75 ns Muon system Muon drift tubes (MDT): performance OK at these rates Cathode strip chambers (CSC): assessment needed Resistive plate chambers (RPC): performance OK at these rates Thin gap chambers (TGC): collection time too long for <25 ns  no good bunch ID Calorimetry LAr: in case of BCO other than 25 ns  need for modification of back-end electronics Trigger/DAQ LVL1 need to be changed 12.5 ns will require significant modification on electronics 15 ns requires significant additional amount of work and costs for electronics modification (FE), but possible 10 ns in addition we (might) get problems with the intrinsic resolutions for part of the muon system Need for decision on BCO for SLHC (impact on electronics) Possible BCO modification

  13. No major upgrade expected but Expected hit rate at 1035 100 – 1000 Hz/cm2 High rate degradation expected on Position resolution Efficiency (800 ns artificial dead time) Ref: talk of Kawamoto at the CERN upgrade workshophttp://agenda.cern.ch/fullAgenda.php?ida=a045387 Muon system

  14. Pileup in LAr Calorimeter (1) • Shaper : optimizes signal to noise ratio between electronics noise and pileup noise • Differentiation to Remove long trailing edge of Lar signal • Electronics : ENI = A/tp3/2 + B/√tp • Pileup : ENE = C√tp • Vary with location and luminosity… Pileup at 1035

  15. ATLAS LAr signal Slower Digital Filtering Max Noise A = (0.17, 0.34, 0.4, 0.31, 0.28) Noise after digital filtering Noise with optimal analog filtering Faster Digital Filtering A = (-0.75, 0.47, 0.75, 0.07, -0.19) Pileup in LAr Calorimeter (2) • Digital filtering to adapt to luminosity [NIM A338, LArg-080] • Slow down or accelerate shaping to adapt from 1033 to 1035 • Runs without any change at 1035… • 2 sets of optimal filtering coefficients if operated at 80MHz • Increased sensitivity to detector parasitics (inductance) : affects constant term Ref: talk of De la Taille at the CERN upgrade workshophttp://agenda.cern.ch/fullAgenda.php?ida=a045387

  16. Impact of BCO on LAr Calorimeter • TTC electronics in the front-end • Any deviation from 40 MHz would require replacement of components (crystals / QPLL) substantial work • Read-out links speed limited to 32-bit/40 MHz • Any BCO frequency > 40 MHz would lead to combining several crossings in one data sample • Extra processing power necessary to disentangle them  change of back-end electronics

  17. Presentation Overview • Motivations and expected schedule • Organisation of upgrade activities • Main changes expected • Upgrade of Inner Detector for SLHC • Developments in Electronics for the Tracker • Conclusions

  18. Upgrade of Inner Detector • Present technologies • Gaseous straws for 50 <R< 80 cm (TRT) • Silicon strips (6 – 12 cm long) for 20 <R< 50 cm (SCT) • Pixels (50 x 400 µm) for 6 <R< 20 cm (SCT)

  19. Initial tracking idea for SLHC • Overall concept: all silicon tracker • Replace • TRT by long silicon strips • SCT by short silicon strips • Pixel tracker by smaller silicon pixels • Several ideas being developed now, no final decision made yet

  20. One possible upgraded ID • Make barrel longer (reducing material services between barrel and endcaps) • Ref: talk of Allport at Genova tracker upgrade workshop http://agenda.cern.ch/fullAgenda.php?ida=a053875 Including fwd disks this would lead to: Pixels: 4.5 m2 ~300,000,000 ch. Short strips: 40 m2~27,000,000 ch. Long strips: 251 m2~15,000,000 ch. Straw man layout: Pixel: z=±50 cm, r=6,15,24 cm 50 x 400 & 50x300 µm2 Mini Strips: z=±144 cm, r=35,48,62 cm axial 50µm x 3 cm Long Strips: z=±144 cm, r=85 & 105 cm stereo 80µm x 9 cm

  21. ID subdivison and SLHC dose Ref: talk of Allport at Genova tracker upgrade workshop http://agenda.cern.ch/fullAgenda.php?ida=a053875 Ref: talk of Vossebeld at RD50 workshop Nov 2005 http://rd50.web.cern.ch/rd50/7th%2DWorkshop/

  22. SCT barrel module Development “stave model” • Stave model • Multi-module structure for barrel • Integrated services • First approach • Starting with ministrips (3 cm) • Hybrid configuration like in present SCT barrel module Ref: talk of Allport at Genova tracker upgrade workshop http://agenda.cern.ch/fullAgenda.php?ida=a053875

  23. Alternative stave model • Integrated services • Peek cooling channels with CF cooling • Operating at < -25 °C (strips) and -30 °C (microstrips, pixels) • Also power and control lines integrated •  power interface and bus drivers needed • R&D proposal issued • https://edms.cern.ch/document/713247/1 Ref: talk of Haber at Genova tracker upgrade workshop http://agenda.cern.ch/fullAgenda.php?ida=a053875

  24. 2 Fluence p/cm 15 16 16 16 8 10 1.6 10 2.4 10 3.2 10 0 100 3x1015 p/cm2 10 years LHC at 1034 cm-2s-1 At r=4cm 1.8x1016p/cm2 10 years SLHC at 1035cm-2s-1 At r=4cm 3Dc PRELIMINARY Ref: Cinzia Da Via 80 60 3D silicon C. DaVia et al. March 06 Signal efficiency [%] 40 20 n-on-p strips P. Allport et al. IEEE TNS 52 (2005) 1903 n-on-n pixels CMS T. Rohe et al. NIMA 552(2005)232-238 0 15 16 16 16 0 5 10 1 10 1.5 10 2 10 2 Fluence [n/cm ] Detector R&D for R< 20 cm3D sensor development • Fast charge collection • Lower Vdepl • But higher capacity • Radhardness considerably better than standard silicon • Until now fabricated on a small scale in house (Stanford) • Yield now 80% • Arrangements for commercial production at SINTEF (still in early state) Ref: talk of Parker at Genova tracker upgrade workshop http://agenda.cern.ch/fullAgenda.php?ida=a053875

  25. Presentation Overview • Motivations and expected schedule • Organisation of upgrade activities • Main changes expected • Upgrade of Inner Detector for SLHC • Developments in Electronics for the tracker • Conclusions

  26. Electronics for the Tracker Three domains of activity • Power distribution • Read-out Links • Front-end electronics

  27. Services • Services in the current detector are a real pain

  28. Power Distribution • The number of channels in the tracker is going to increase • The electronics technology will need less power but not less current • What is a pain today will be an unsolvable problem • Two alternatives looked at • DC-DC converters • Serial powering Source: 9/2002 GEANT-4 simulation by D. Constanzo Pixel detector material budget

  29. DC-DC Convertors • On-going development of switched capacitor converters • Conversion Ratio 5-to-1, using a 0.35 µm technology, at an operating frequency of 5Mhz • Voltage efficiency ~.84 • Current efficiency ~.92 • Ripple = 1.2% • Output impedance = 0.25 ohms (25mv / 100ma) Ref: talk of Ely at Genova tracker upgrade workshop http://agenda.cern.ch/fullAgenda.php?ida=a053875

  30. constantvoltage constantvoltage constantvoltage constantvoltage Powerlines Modules constantcurrent TWO powerlines Modules 10V 7.5V 5V 2.5V 0V Serial Powering • Currently used Parallel Powering: • Idea of Serial Powering:

  31. on chip LinReg ShuntReg Shunt regulator Linear regulator FE core FE core Shunt regulator Linear regulator FE core FE core Serial Powering (cont.) • Basic principle: • Constant current through all modules • Voltages generated on FE chip by • Shunt regulators • Linear regulators FE chip

  32. Serial Powering (cont.) • Tests done with SCT (4 modules) and Pixel (6 modules) have shown no effect on noise • Still a lot of issues to be looked at • Loss of a regulator • Floating modules • AC coupled or optics read-out Ref: talks of Weber and Grosse-Knetter at Genova tracker upgrade workshop http://agenda.cern.ch/fullAgenda.php?ida=a053875

  33. Read-out Links • In the current tracker there are 3 types of read-out links • Two optical links at 40 and 80 Mbits/s for SCT and Pixel • 40 Mbits/s copper links and Gbit optical link for the TRT • Strong wish to define at least common building blocks and opto-packages • First questions: • Which read-out architecture? • Which speed?

  34. Expected data rate at SLHC A few Gbit/s look OK Read-out architecture to be looked at to find common building blocks Straw Man Lay-out

  35. Opto-Links: Current activity • One R&D project presented and approved • https://edms.cern.ch/document/694105/1.05 • Radiation testing of existing devices and of COTS • Include VCSELs, PIN Diodes and also serialisers • Strong wish to collaborate actively with CMS • Common forum put in place Ref: talk of at Genova tracker upgrade workshop http://agenda.cern.ch/fullAgenda.php?ida=a053875

  36. Front-end electronics • Need to follow technology trends • Radiation hardness is a key issue • Strong interest in very deep sub-micron technologies • Development of a pixel read-out chip already started • Could be used for the B-Layer replacement • Production to be done in 2010 for an installation in 2012 Ref: talk of Einsweiler at Genova tracker upgrade workshop http://agenda.cern.ch/fullAgenda.php?ida=a053875

  37. Silicon Strip Read-out • R&D proposal: development of a CMOS 0.25 read-out chip (ABC-Next) compatible with the existing one (ABCD) • to prepare a design of the front-end ASIC in deep submicron radiation tolerant technology • to implement functional blocks and circuit options required for new designs of modules and staves being developed for the upgrade Inner Detector • Fully compatible with existing read-out system • To be used for testing detector and architecture choices: • Able to accept both signal polarity • Implementation of on-chip power regulation systems to enable the design of detector modules powered through DC-DC converter or serial powering schema • Faster read-out capability • DC balanced protocols for possible AC coupling • Tools for capability of concentrating several read-out links on a Gbit serialiser Ref: R&D proposal https://edms.cern.ch/document/713247/1

  38. ABC-Next Proposal • Design in 2006 • To be used on stave prototypes as from 2007 Shunt and Linear regulators to be included ABC-Next Block Diagram

  39. Next steps for the strips read-out • ABC-Next in 0.13 CMOS technology • Year 1 is (should be) 2006

  40. J. Kaplon et al., 2004 IEEE Rome Oct 2004, use 0.25 mm CMOS For CMOS: Input transistor: 300 mA, other transistors 330 mA (each 20 – 90 mA) SiGe Option • Interest for the SiGe option • Main motivation being the possible power saving at the preamplifier stage

  41. CHIP TECHNOLOGY FEATURE  0.25 mm CMOS ABCDS/FE J. Kaplon et al., (IEEE Rome Oct 2004)  IBM enhanced 5HP SiGe Power: Bias for all but front transistor 330 mA 0.8 mW 8*5mA= 40 mA(conservative) 0.1 mW  Power: Front bias for 25 pF load 300 mA 0.75 mW 150 mA 0.375 mW Power: Front bias for 7 pF load 120 mA 0.3 mW 50 mA 0.13 mW Total Power (7 pF) 2x1015 0.23mW 1.1 mW 0.48 mW Total Power (25 pF) 3x1014 1.5 mW SiGe Benefit • Cost and yield (for large area chips) may be a problem Ref: talk of Grillo at Genova tracker upgrade workshop http://agenda.cern.ch/fullAgenda.php?ida=a053875 Ned Spencer’s talk this week

  42. Summary of Developments • On-going developments or tests • Serial powering • DC-DC converters • Pixel front-end chip in 0.13 CMOS • Strip front-end in SiGe • “Official” R&D proposal • Radiation hardness of existing links components (approved) • Stave development (being reviewed) • ABC-Next read-out chip (being reviewed)

  43. Conclusions • ATLAS upgrade activities have been started up • Aim for completion: 2015 • The R&D and development phase must be faster than in the past • Selection process to be defined and agreed upon • Schedule is a key element • Major activity is the replacement of the complete Inner Detector • Other sub-detectors require less dramatic changes • Big number of silicon strip modules (20k vs 4k now) • Electronics R&D in power distribution, read-out links and front-end designs

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