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Boolean Algebra (Continued)

Boolean Algebra (Continued). ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning. Exclusive-OR (XOR). XOR Theorems. Equivalence. Equivalence (XNOR). Project 1. Combinational Circuit Analysis Determine input/output relationship of function

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Boolean Algebra (Continued)

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  1. Boolean Algebra (Continued) ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning

  2. Exclusive-OR (XOR) 311_03

  3. XOR Theorems 311_03

  4. Equivalence 311_03

  5. Equivalence (XNOR) 311_03

  6. Project 1 • Combinational Circuit Analysis • Determine input/output relationship of function • Boolean Equation • Truth Table • Implement logic circuit with FPGA • Schematic capture design tools • Test circuit to verify operation • Project Report • Teams of 2 persons 311_03

  7. Xilinx ISE Design Suite • Enter description of logic circuit • Schematic editor • VHDL • Use a logic synthesizer to generate a netlist • Use implementation tools to map logic gates and interconnections into the FPGA • Generate a bitstream programming file • Configure device • Download the bitstream to the FPGA chip 311_03

  8. Schematic or 311_03

  9. 311_03

  10. File → New Project Project Name Demo1 Project Location C:\xxx\xxx Top-Level Module Type Schematic Device Family Spartan3E Device XC3S100E Package TQ144 (BASYS) CP132 (BASYS 2) Speed Grade -5 New Project 311_03

  11. Project → New Source Schematic Demo1 Schematic Editor Symbols Category list Symbol list Drawing area Tools Add wire Add I/O marker New Source 311_03

  12. add wire add I/O marker 311_03

  13. Categories Logic Symbols and2 and3 inv or2 Add wires Point to point Stubs I/O Markers Input marker Output marker Rename Port Demo1 Schematic 311_03

  14. FPGA LEDs Switches 311_03

  15. FPGA Pins 311_03

  16. Constrain the Design • User Constraints → I/O Pin Planning – Pre-Synthesis • Implementation Constraints File • Demo1.ucf • PlanAhead • I/O Ports • Site 311_03

  17. Synthesize & Implement • Synthesize Design • Implement Design • Generate Programming File 311_03

  18. BASYS Configuration Set to ROM 311_03

  19. Configure Device • Configure Device (Adept) • Initialize Chain • XCF02S (PROM) • demo1.bit • Program • Cycle Power (Reset) 311_03

  20. 311_03

  21. Test the Design XY F 1 X Y Z 0 311_03

  22. Project Report • Cover Sheet • Project Name/Number • Authors • Professor’s Initials • Objectives • Discussion • Boolean Equation • Truth Table • Circuit Schematic • Conclusion • Test Results 311_03

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