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DPL Thermal Model of Test Microchip Structure without Cavity Dedicated to Estimation of Nanoelectronic Circuits Thermal Properties. 2 2 nd International Workshop on Thermal Investigation of ICs and Systems ( Therminic 201 6 ) , Budapest , Hungary , September 21 – September 23, 20 16.

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  1. DPL Thermal Model of Test Microchip Structure without Cavity Dedicated to Estimation of Nanoelectronic Circuits Thermal Properties 22ndInternational Workshop on Thermal Investigation of ICs and Systems (Therminic2016), Budapest, Hungary, September21 – September 23,2016 T. Raszkowski, M. Zubert, A. Samson, M. Janicki, A. NapieralskiDepartment of Microelectronics and Computer Science, LodzUniversity of Technology Wolczanska 221/223, 90-924 Lodz, Poland e-mail: mariuszz@dmcs.p.lodz.pl Łódź University of Technology Department of Microelectronics and Computer Science 1/23

  2. Agenda 1 Problem description 2 Analyzed problem 3 Numerical solution of the problem 4 Simulation results 5 Conclusions Łódź University of Technology Department of Microelectronics and Computer Science 2/23

  3. Problem description General heat transfer behaviourdescribedusingFourier-Kirchhoff(F-K) equation (1822): cv – volume-specificheat T – temperaturefunction k – thermal conductivity q – heatflux Łódź University of Technology Department of Microelectronics and Computer Science 3/23

  4. Problem description The F-K equation postulates some nonphysical behaviours: heat propagates with infinite speed(e.g. for free and 2nd B.C.), both heat flux and temperature gradient are changing instantaneously, what does not agree with experiments[1][2], [1] Hebboul S.E. and WolfeJ.P. . Lattice dynamics of insb from phonon imaging. ZeitschriftfürPhysik B Condensed Matter, 73(4):437-466, 1989. [2] Gutfeld R.J. and Nethercot A.H.Heat pulses in quarto and sapphire at low temperatures.Phys. Rev. Lett., 12:641, 1964. Łódź University of Technology Department of Microelectronics and Computer Science 4/23

  5. Problem description Moreover: • semiconductormanufacturing technologycauses extreme miniaturization of electronic devices e.g.: • 12-14nm (Intel Broadwell CPU family, Samsung Exynos 7420 etc.), • 6nm (in the prototype FinFETs technology[3]), • nanowire and nanotube fabrication. In all of these cases the dimensionless Knudsen number, expressed as: Kn=(the mean free path) / (the structure characteristic length) >> 1 where(the mean free path)≈ 41.8nm at 300 K[4]. [3] A. Kaneko, Y. Tsunashima et al. Sidewall transfer process and selectivegatesidewall spacer formation technology for sub-15nm finfetwithelevatedsource/drainextension. In Electron Devices Meeting, 2005. IEDM TechnicalDigest. IEEE International, pp. 844-847, Dec 2005. [4] Aydin Nabovati, Daniel P. Sellan, and Cristina H. Amon. On thelatticeboltzmannmethodfor phonon transport. Journal of ComputationalPhysics, 230(15):5864 - 5876, 2011. Łódź University of Technology Department of Microelectronics and Computer Science 5/23

  6. Numerical Solution (Intel Broadwell and Haswell, Samsung 14nm LPE) • 3D structure developed using quadruple Fin-FET based on 14 nm Samsung LPEtechnology • Fin-FET properties: 14nm Łódź University of Technology Department of Microelectronics and Computer Science 6/23

  7. Simulation Results • The sample temperature distribution in Fin-FET • Comparison of average normalizedtemperature in Fin-FET channel obtained using DPL and FK models DPL FK The temperature isoverestimated by classicalF-K model! Łódź University of Technology Department of Microelectronics and Computer Science 8/23

  8. Problem description 100nm 100nm SiO or Si N 2 3 4 100 - 500nm SiO or Si N 2 3 4 1 - 5um nanothermometer Pt Si – 400um Passivation layer (SiO ) 2 100 – 500nm SiO or Si N 2 3 4 Pt resistors , thickness 30 -50nm - Si – 400nm air heater Al ( or p ) + Goal: The test chip design for theestimation of the DPL model parameters of electronics materials (τt, τq, etc). The cross-sectional view of the nanosized horizontal structure consisting of polysilicon resistors The cross-sectional view of the vertical structure with the air chamber filling Similar investigations for 1-D structures and spectral methods: JoseOrdóñez-Miranda, J. J. Alvarado-Gil. Determination of Time-Delay Parameters in the Dual-Phase Lagging Heat Conduction Model. Journal of Heat Transfer 132(6),June 2010 Łódź University of Technology Department of Microelectronics and Computer Science 11/23

  9. The thermal model of the test chip dedicated for the DPL model parameters estimation τt, τq • Cross-sectionview of part of nano-sizedstructure(not to scale) • Cross-sectionview of entirenano-sizedstructure(not to scale) For the remaining part of structure: • the Neumann BC isimposed, • thermalcapacitanceisneglected, • resistanceisconsideredonly. Łódź University of Technology Department of Microelectronics and Computer Science 12/23

  10. Thermal Simulation (FEM) • One resistor (red color) isheated. • The secondresistor (greencolor) is a thermometer. • TheF-Kand DPL model areused to modelling of the temperaturedistribution in the structure. • Structurematerialproperties: • In order to obtain the solution, the Finite Element Method (FEM) isused. • Discretization meshcomposedof 3528 triangles(not to scale): • Maximum area of single triangle: • 4 nm2 (top layer) • 2 500 nm2 (middlelayer) • 10 000 nm2 (bottomlayer) Łódź University of Technology Department of Microelectronics and Computer Science 13/23

  11. SimulationResults (FEM) • Comparison of the temperaturerisein heatsource and in thermometerusingF-Kmodel • Finalsteadystatesolution • Comparison of the temperaturerisein the heatsource and in thermometerusing DPL model Łódź University of Technology Department of Microelectronics and Computer Science 14/23

  12. SimulationResults (FEM) • Comparison of the temperaturedistribution in investigatedstructure for chosen time instantsobtainedusingbothF-Kand DPL models • Comparison of the temperaturerisein heatsource and in thermometerusingbothF-Kabd DPL models Łódź University of Technology Department of Microelectronics and Computer Science 15/23

  13. PreliminaryConclusions (FEM) • Temperatureriseinheatedresistorhas big influence on the growth of thetemperatureinthermometer. • Averagetemperaturedifferencesbetweenresistorsaresmall. • F-Kmodel causesfastertemperaturerisethan DPL one. • The temperature is overestimated by classicalFK model! • Comparisonof the temperaturerisein heatsource and in thermometerusingboth FK abd DPL models Łódź University of Technology Department of Microelectronics and Computer Science 16/23

  14. Heat transfer theory Dual-Phase-Lag (DPL) model proposed by Tzou (1995): cv – volume-specificheat T – temperaturefunction q – heatflux k – thermal conductivity τT – heatflux time lag L – slab thickness τq – heatfluxtemperature lag Łódź University of Technology Department of Microelectronics and Computer Science 17/23

  15. Mathematical Problem Formulation • Cross-sectionview of part of nano-sizedstructure(not to scale) Łódź University of Technology Department of Microelectronics and Computer Science 18/23

  16. Mathematical Problem Formulation The mirrored structure Theimmaginareheatsource (Q0) von Neuman B.C. Theheatsource (Q0) Theprobe (TB) The main structure Natural outside B.C. (Text=0) Łódź University of Technology Department of Microelectronics and Computer Science 19/23

  17. Mathematical Problem Formulation The mirrored structure Theimmaginareheatsource (Q0) H von Neuman B.C. H=2·100nm-50nm=150nm Theprobe (TB) Theheatsource (Q0) The main structure Natural outside B.C. Łódź University of Technology Department of Microelectronics and Computer Science 20/23

  18. Mathematical Problem Formulation Dual-Phase-Lag (DPL) model proposed by Tzou (1995): Theprobe (TB) Theheatsource (Q0) Natural outside B.C. Łódź University of Technology Department of Microelectronics and Computer Science 21/23

  19. Mathematical Problem Formulation Dual-Phase-Lag (DPL) model proposed by Tzou (1995): T – temperaturefunction q – heatflux Theheatsource (Q0) cv – volume-specificheat Theprobe (TB) k – thermal conductivity τT – heatflux time lag τq – heatfluxtemperature lag Natural outside B.C. Łódź University of Technology Department of Microelectronics and Computer Science 22/23

  20. ProposedAnalitycalSolution Łódź University of Technology Department of Microelectronics and Computer Science 23/23

  21. ProposedAnalitycalSolution Łódź University of Technology Department of Microelectronics and Computer Science 24/23

  22. ProposedAnalitycalSolution Łódź University of Technology Department of Microelectronics and Computer Science 25/23

  23. The First Solution (F-K) where Łódź University of Technology Department of Microelectronics and Computer Science 26/23

  24. The First Solution (F-K) where Łódź University of Technology Department of Microelectronics and Computer Science 27/23

  25. The First Solution (F-K) where Łódź University of Technology Department of Microelectronics and Computer Science 28/23

  26. The First Solution (F-K) Łódź University of Technology Department of Microelectronics and Computer Science 29/23

  27. TheSecondSolution (mDPL) Dual-Phase-Lag (DPL) model proposed by Tzou (1995): B =τT/(2 ∙τq) B =0.5 – the Fourier-Kirchhoff solution B→0 – the hyperbolic solution B>>0.5 – the heat transfer observedinnanoscale τT – a heatflux time lag t t+τq t+τT τq – a heatfluxtemperature lag τT=60 ps τq=3 ps Łódź University of Technology Department of Microelectronics and Computer Science 30/23

  28. TheSecondSolution (mDPL) Łódź University of Technology Department of Microelectronics and Computer Science 31/23

  29. The First Solution (F-K) Łódź University of Technology Department of Microelectronics and Computer Science 32/23

  30. Mathematical Problem Formulation • Cross-sectionview of part of nano-sizedstructure(not to scale) Łódź University of Technology Department of Microelectronics and Computer Science 33/23

  31. Conclusions Thermal analyses of modern FinFET structure, including the three-dimensional approximation of the DPL equation, using the no-meshFinite Difference Method, havebeenmade. TheSimulation results prove that FinFETs can work in longer time horizon due to the fact that temperatures in FinFET channels are lower than expected ones. Łódź University of Technology Department of Microelectronics and Computer Science 34/23

  32. EmpiricalDiffusionDescription Dual-Phase-Lag (DPL) model: Porous Medium Equation(PME): k=k1·T+k0 Barenblatt &Zel’dovich (1950), alsoVázques(parabolic, eikonalequation) Łódź University of Technology Department of Microelectronics and Computer Science 35/23

  33. MathType fonts: Euclid 12345abcd+-/., Eucsym12345abcd+-/., euextra12345abcd+-/., eufrak12345abcd+-/., eumat1 12345abcd+-/., eumat1b 12345abcd+-/., eumat2 12345abcd+-/., eumat2b 12345abcd+-/., fences 12345abcd+-/., mtextra12345abcd+-/., Thankyou for attention! Łódź University of Technology Department of Microelectronics and Computer Science 36/23

  34. Results and DPL vs MD/BTE comparison • Silicon properties: • Lattice constant: a=5.43 Angstrom=0.543 nm • Phonon mean free path: 76 Angstrom (electron)≈14 a 55 Angstrom (hole) ≈10 a • Nano-transistor gate length: 9÷20 nm=9÷20∙10-9m ≈16÷37 a Simplification! N=16÷37 1 Heatflow The Fourier-Kirchhoff diffusiveequation cannot be directly used in case of nanotubes, nanowires, molecurals and other nanotransistors. Łódź University of Technology Department of Microelectronics and Computer Science 37/23

  35. Results and DPL vs MD/BTE comparison • The Green-Kubo formalism tells us that thermal conductivity is determined according to thefollowing expression: • The temperature is typically calculated based on virial theorem: • The current density is also calculated as an average value. N 1 Heatflow Łódź University of Technology Department of Microelectronics and Computer Science 38/23

  36. Results and DPL vs MD/BTE comparison The Heat Transport in Nano-electronic Elements LeftLangevinbathRightLangevinbath MolecularDynamicsimulation: Łódź University of Technology Department of Microelectronics and Computer Science 39/23

  37. Results and DPL vs MD/BTE comparison • Molecular Dynamics simulation (MD) • Schrödinger Equation (SE) • Boltzmann Transport Equation (BTE) • Macroscopic Energy Treatement using Fourier-Kirchhoff equation (ME) • Ballistic - Diffusion Equation (BDE – dotted region) • The Intel CPU Broadwell (14nm, 2.9GHz) and Haswell (22nm, 4.4GHz) Łódź University of Technology Department of Microelectronics and Computer Science 40/23

  38. MathType fonts: Euclid 12345abcd+-/., Eucsym12345abcd+-/., euextra12345abcd+-/., eufrak12345abcd+-/., eumat1 12345abcd+-/., eumat1b 12345abcd+-/., eumat2 12345abcd+-/., eumat2b 12345abcd+-/., fences 12345abcd+-/., mtextra12345abcd+-/., MathType fonts: Euclid 12345abcd+-/., Eucsym 12345abcd+-/., euextra 12345abcd+-/., eufrak 12345abcd+-/., eumat1 12345abcd+-/., eumat1b 12345abcd+-/., eumat2 12345abcd+-/., eumat2b 12345abcd+-/., fences 12345abcd+-/., mtextra 12345abcd+-/., Łódź University of Technology Department of Microelectronics and Computer Science

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