Microelectronics System Design for Chronic Brain Implants

1. Microelectronics System Design for Chronic Brain Implants ECEN 5007 S. Johnson, V. Ganesan 12-10-02

2. Motivation • Research in the area of nueronal signaling is constrained by the test electronics readily available. • Large, inflexible neural probes are implanted into test animals, requiring bulky cabling configurations to connect to the recording equipment. • Such a test setup hampers the test subject's movement and thus greatly changes the way in which the test subject would normally interact with its environment. • This change in normal behavior effects the way in which they learn and in turn can skew desired test results. • A proposed solution is to place the microelectronics used for recording neural signals onto a small chip, which rides on top of the mechanical probe. • Such a device would be small enough to be implanted, and allow the test animal to recover from the surgery and soon after interact normally with its environment.

3. Key System Requirements • No chronic external wiring - External wiring interferes with the natural movement and hence behavior of the test subject • The probe must be able to "float" with the tissue in which it is implanted - The brain moves inside the skull, an implant that is rigid and anchored to the skull does not allow for such movement, hampering normal function. • The electronics must be integrated with the mechanical probe - Proximity to the acquired signal helps keep noise low (short transmission path) and aids in a higher resolution of data. • Low power consumption - Must keep power consumption low to minimize energy storage (battery) 1mW goal. • Low power dissipation - Must keep power dissipation low to reduce heat load on tissue. (A rise in temperature of 0.5C causes stress in the tissue disrupting normal function, a 2C rise causes tissue death). • Small size - Chip must be small so as not to interfere with normal function. For this application the area of tissue is 3mm2, and the mechanical probe and acquisition electronics must fit within a 1mm2 footprint.

4. System Description • For the purposes of this project, the focus will be the Probe Module. • The Surface Module is a larger chip where the majority of signal processing will take place. It is attached to the outside of the scull of the test animal where constraints of size, power consumption and power dissipation are not as great. • The Surface Module provides an interface to the researcher to access data, charge the on-chip battery cell, and send simple control commands to the electronics. • A flexible wire tether bundle would provide the interconnections between the two modules . The Surface Module is shown only for completeness of the system.

5. Signal Acquisition The signal acquisition portion of the Probe Module is comprised of an analog front end, a multiplexer, and an ADC. The analog front end interfaces with sixteen probe lines, and amplifies the incoming neural signals. The first amplification stage is the LNA (low noise amplifier) and is shown below.

6. LNA (Low Noise Amplifier) • An AM (amplitude modulation) block which shifts the low frequency, low voltage signal up in frequency above the flicker noise of the preamp, • A low noise pre-amp • A Selective Amplifier (acting as a bandpass filter with gain, which filters out the low frequency noise component, leaving the modulated signal component) • A second AM block which demodulates the original signal back to its baseband frequency. • An LPF filter which filters out the additional, high frequency, modulation components. • The second amplification stage is the Instrumentation Amplifier. It's purpose is to further amplify the desired neural signal to a level required by the digital processing electronics, or ADC block.

7. Low Noise Pre-Amplifier and Selective Amplifier • The Selective amplifier is realized by 2 amplifiers low noise rail-to-rail preamplifier followed by a 2nd order band pass (GmC) filter. • The pre-amp amplifies both the noise and modulated input signal. It requires a minimum corner frequency equal to the chopper frequency, and a high CMRR • The Gm-C (bandpass) filter reduces residual offset from charge injection of input modulator. It requires a matching oscillator to maintain a constant Gm.

8. Low Noise Pre-Amplifier Fully Differential Op Amp Supply voltage: 2V Bias Current: 2uA Power Dissipation: ~700uW Circuit Area: 913 um2 (< 0.1% total chip area) Common Mode Feedback Circuit Improvements Further optimize bias current, supply voltage and device sizes. Investigate/simulate different op amp topologies (i.e. telescopic)

9. Low Noise Pre-Amplifier Gain = 36dB Phase = -93.2 degrees fM ~ 86 degrees Corner Frequency 60.25 kHz Cross Over Frequency 3.75 MHz

10. Low Noise Pre-Amplifier Input Signal - 60kHz, 1mV Output Signal - 60kHz, 48mV Gain at Corner Frequency ~ 33.6dB

11. Filter Design • Aims to reduce the dc offset from charge injection of the input modulator. • Input Gm converts input signal from voltage to current mode • Gm2 and Gm3 constitute resonant stage which determines the center frequency of the filter. • Gm4 converts the signal from current to voltage mode

13. Filter design contd • A(s) = Ao wo s / ( s2 + wo s / Q + wo2 ) • wo = √ (( gm2 + gm4 gmo2) / c2 ) is the resonance frequency • Q = gm/ gm4 is the quality factor • A0 = gm1 / gm is the filter gain • C is larger than the parasitic caps • Q is chosen around 4 and 5

14. Gm Cell • Linearity transconductor using 2 triode region transistors as source degeneration resistor is used in the filter. • Gm = Io / ( v1 – v2 ) = • 1 / ( Rs1 + Rs2 + ( Rds3 || Rds4 )

15. Gm contd • Rs1 = output impedance of input transistor viewed from source • • Rs1 = 1/ gm1 • where gm = √ ( 2up Cox (W/L)Id ) • Rds3 = 1/ gds3 • Where gds3 = up Cox (W/L) Veff • Taking gm1 = gm2 and gds3 = gds4 • Gm = gm1 / 2 || 2 gds3 = 4 gm1 gds3 / ( gm1 + 4 gds3 )  

16. CMFB • For fully differential circuitry we stabilize the operating point with the differential feedback loop.

17. The Gm-C filters are sensitive to parasitic capacitances due to lack of low impedence nodes and this causes the variation in the time constant of the filter Frequency drift causes Gm to shift. Want a constant Gm value To get rid of the time constant variation we track it with on-chip chopper freqency. Tracking with off-chip reference clock will cause more variations due to temperature and process parameter changes Matching Oscillator

18. Oscillator • The GNL block ensures oscillations and regulates the signal amplitude. • W = √ (gm2 – ( gn1 / 2 ) 2 ) / C

19. Gm- C filter • Supply Voltage : 3V • Bias Current • Gm1 20uA • Gm 25uA • Gm 50uA • Power Dissipation 400uW • Circuit area = 1380 um sq.

20. Multiplexer • Once the signal is amplified, it is multiplexed with the other amplified probe lines. • The multiplexer's purpose is to sample each of the lines at a minimum of 25kHz. • This satisfies the Nyquist criterion where the sampling rate must be at least twice that of the signal being sampled. • For this application, the neural signal bandwidth is less than 5kHz. Since the system can obtain good data from up to sixteen probes at one time, the switching frequency of the multiplexer must be a minimum of 400kHz to achieve a 25kHz sampling rate for each line. • The ADC is the final block of the signal acquisition section of the Probe Module. It digitizes the multiplexed data stream for transport to the Surface Module.

21. Configuration and Control • Upon initial power-up and data acquisition, the researcher will determine which probe signals are useful. • The researcher sends a code to the Configuration and Control block on the Surface Module, telling it which channels are good. • The "good" channel information is sent as a binary stream to the Configuration and Control block on the Probe Module. The Control block then powers down the amplifier stages whose signals are too weak or non-existent, thus saving on power consumption and lowering power dissipation.

22. Clock Circuit Ring Oscillator 40kHz non-overlapping clock used for the modulators Circuit for non-overlapping clocks

23. Project Scope • The Analog Front-End will be composed of at least four input lines from the mechanical probe. • A minimum signal level for each of these lines is expected to be 100uV. The circuit begins with all probe amplification lines powered on. • The clocking for the modulator blocks is set to achieve a modulation frequency of approx. 40kHz. • The Configuration and Control block will be given a command (binary bit stream) that it must interpret and power down those amplification stages that are not needed, shutting off particular probe lines. It then relays the sequence of probe lines to be sampled to the multiplexer. • The switching frequency of the multiplexer is set knowing the number of probe lines to be sampled (25kHz minimum sampling per line). • The output from the amplified lines is expected to have a 60dB voltage gain (100uV to 100mV). Power consumption for the system is targeted at 1mW.

24. System Overview - Ideal LNAs 00 01 10 11

25. Binary Counter

26. Simulation Results All LNAs enabled LNA 2 (400Hz sinewave) LNA 1 (200Hz sinewave) LNA 0 (100Hz sinewave) sw 3 - on LNA 3 signal sw 0 - on LNA 0 signal sw 2 - on LNA 2 signal sw 1 - on LNA 1 signal LNA 3 (800Hz sinewave)

27. Simulation Results LNAs 0 and 2 enabled LNA 2 (400Hz sinewave) LNA 0 (100Hz sinewave) LNA 3 (800Hz sinewave) LNA 1 (200Hz sinewave)

28. Chopper Amplifier Input Signal Amplifier LPF Modulator BPF Demodulator Simulated Noise

29. Chopper Amplifier (Analog Blocks)

30. Chopper Amplifier (Analog Blocks) Input Signal 100uV, 4.5kHz Output Signal ~100mV, 4.5kHz

31. System Overview - CHopper Simulated Noise CHopper Amplifier (LNA 0) Modulator Clocks Input Signal

32. Simulation Results (Ideal) LNA 2 (400Hz sinewave) LNA 1 (200Hz sinewave) CHopper LNA 0 (4.5kHz sinewave) CHopper LNA before and after multiplexer All LNAs enabled LNA 3 (800Hz sinewave)

33. Simulation Results (Analog Blocks) 4.5kHz Signal Channel 3 - Purple (Ideal) 4.5kHz Signal Channel 0 - Yellow Channel 0 w/ analog blocks Channels 1-3 Ideal