Heuristics for Reversible logic synthesis

1. Heuristics for Reversible logic synthesis Speaker: Min Lung Chuang Advisor: Chun-Yao Wang 2005/06/22

2. Outline • Introduction • A simple PPRM form heuristic • A SBDD with complemented edge heuristic • Experimental results • Conclusion

3. Reversible Circuit • Reversible circuits have applications in - low power design - quantum computer Landauer Principle If a computation process erases a single bit of information, the energy dissipated into the environment is at least E = k T ln2 , where k is the Boltzmann’s constant, • T is the temperature quantum computing is a reversible computing

4. Outline • Introduction • A simple PPRM form heuristic • Introduction • Algorithm • A SBDD with complemented edge heuristic • Experimental results • Conclusion

5. Synthesis of Reversible Logic Abhinav Agrawal and Niraj K.jha

6. Outline • Introduction • A simple PPRM form heuristic • Introduction • Algorithm • A SBDD with complemented edge heuristic • Experimental results • Conclusion

7. PPRM Expansion (1/2) • Arbitrary product terms combined by EXORs are called ESOP (Exclusive-or-Sum-of-Products) Expression. Ex: is an ESOP. • The positive-polarity Reed-Muller expansion uses only uncomplemented variables in ESOP expression. Ex: • The PPRM of a function is unique and of the form:

8. Problem Formulation (2/2) • EX: IF there is a reversible function:

9. Outline • Introduction • A simple PPRM form heuristic • Introduction • Algorithm • A SBDD with complemented edge heuristic • Experimental results • Conclusion

10. Synthesis algorithm flow chart (1/8) Store PPRM expansion of function in polarity queue Pop node with highest priority from priority queue NO More factors? Select possible factor in the node popped YES Substitute factor selected in PPRM expansion of function and from newnode Insert newnode into priority queue Synthesis is complete? NO YES End of algorithm

11. Algorithm (2/8) • EX: There is a reversible function:

12. Synthesis algorithm flow chart (3/8) Store PPRM expansion of function in polarity queue Pop node with highest priority from priority queue NO More factors? Select possible factor in the node popped YES Substitute factor selected in PPRM expansion of function and form newnode Insert newnode into priority queue Synthesis is complete? NO YES End of algorithm

13. Algorithm (4/8) Substitution in the expansions of all the variables contained in the curnode

14. Algorithm (5/8) • Why we want to substitution in the expansions of every variable？ • We want to make become , so we want to simplify the expansion through these substitution. • We only consider synthesis reversible circuits with generalized Toffoli gate, is not allowed. • is not allowed, because in every reversible gate, the input variable must contained in the output function

15. Synthesis algorithm flow chart (6/8) Store PPRM expansion of function in polarity queue Pop node with highest priority from priority queue NO More factors? Select possible factor in the node popped YES Substitute factor selected in PPRM expansion of function and from newnode Insert newnode into priority queue Synthesis is complete? NO YES End of algorithm

16. Algorithm (7/8) • The priority of newnode is determinedby newnode_priority=α*newnode.depth( )+β*(init_count- newnode.term_count)/newnode.depth( ) the parameter α=0.3, β=0.7 • The first item means that if the depth is larger, the result might be closer. • The second item addresses the primary objective of minimizing the number of gates.

17. Algorithm (8/8) newnode_priority=α*newnode.depth( )+ β*(init_count- newnode.term_count)/newnode.depth( )

18. Outline • Introduction • A simple PPRM form heuristic • A SBDD with complemented edge heuristic • Introduction • Algorithm • Experimental results • Conclusion

19. A New Heuristic Algorithm for Reversible Logic Synthesis Pawel Kerntopf

20. Outline • Introduction • A simple PPRM form heuristic • A SBDD with complemented edge heuristic • Introduction • Algorithm • Experimental results • Conclusion

21. Problem Formulation • EX: If there is a reversible function in PPRM form: • This paper proposes a new complexity measure for reversible logic synthesis based on shared BDD with complemented edges (instead of truth table or PPRM forms, as in the previous algorithm)

22. Outline • Introduction • A simple PPRM form heuristic • A SBDD with complemented edge heuristic • Introduction • Algorithm • Experimental results • Conclusion

23. F1 F2 F3 F4 1 x2 x2 x2 1 0 0 1 0 x1 x1 1 1 0 0 1 shared BDD (1/9) • A share BDD • Represent multiple function into a graph • Share sub-graphs with each other.

24. f f a 0 1 a 0 1 b b 1 0 0 1 b 0 1 c c c 0 1 1 0 1 c 1 0 0 0 1 1 1 0 SBDDwith complemented edges (2/9) • The complemented edge is an attribute which indicates to complement the function of the sub-graph pointed to by the edge. • Reduce computation time • Reduce Memory requirement • Ex: c

25. f f a a f 0 1 0 1 b b a 0 1 0 1 0 1 c c b 0 0 1 1 0 1 1 1 c 0 1 1 SBDDwith complemented edges (3/9) • The complemented edge is an attribute which indicates to complement the function of the sub-graph pointed to by the edge. • Ex:

26. f1 f2 f3 a a a 0 1 0 1 1 0 b b b b 1 1 0 1 1 0 c 0 0 0 1 1 SBDDwith complemented edges (4/9) • SBDD with complemented edges provide a compact representation of multiple-output functions after choosing an appropriate variable ordering. EX:

27. f1 f2 f3 a a a 0 1 0 1 1 0 b b b b 1 1 0 1 1 0 c 0 0 0 1 1 The Complexity Measure (5/9) • The complexity measure D( f ) of an n*n reversible function f is equal to D( f ) = s( f ) – n, where s( f ) denotes the number of non-terminal nodes in the reduced ordered SBDD of f with complemented edges. D( f ) = 8 – 3 = 5

28. The analysis of the complexity measure (6/9) • The Hamming distance between two bit string is the number of position, in which they differ. • The optimal circuit of some reversible function do not form a nonincreasing sequence of the sum of Hamming distance, C( f ). in 000 001 010 011 100 101 110 111 out 001 000 011 010 101 111 100 110 C( f ) = 8

29. a’ a a’ a a’ a a a’ b’ a b b’ b a’ b b’ b b’ c c’ c’ c PRELIMINARIES (7/9) • NOT, CNOT, Toffoli, SWAP and Fredkin gates (in shot, N, C, T, S and F, respectively) are defined as follows :

30. The Logic Operation (8/9) • EX: Fredkin gate

31. Algorithm (9/9) • In every step, all gates are examined and for each of them SBDD is constructed. • Next, we select gates, for which D( f ) of the transformed function is minimal. • If there is more than one such gate, we proceed further with all of them. • In the experiments, the algorithm always terminated with the circuit realizing the given function.

32. Outline • Introduction • A simple PPRM form heuristic • Introduction • Algorithm • A SBDD with complemented edge heuristic • Introduction • Algorithm • Experimental results • Conclusion

33. Experimental results In NCT library

34. Outline • Introduction • A simple PPRM form heuristic • Introduction • Algorithm • A SBDD with complemented edge heuristic • Introduction • Algorithm • Experimental results • Conclusion

35. Conclusion • There are many complexity measure proposed for reversible logic synthesis. • These different complexity measure is used in the same way – greedy approach. • We can try to find a better and different complexity measure for reversible logic synthesis. • In another way, we can try to use these complexity measure in different way. • Extend these heuristics for multi-valued reversible logic synthesis