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TELL1 upgrade meeting

TELL1 upgrade meeting. CERN 28/10/2009. Today. (1) Put on floor all issues related to TELL1 production - Procurement of components - Manifacturing - Testing (2) Discuss pros/cons of a possible (minor) TELL1 upgrade to decide if/how to proceed (3) Identify possible contributors.

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TELL1 upgrade meeting

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  1. TELL1 upgrade meeting CERN 28/10/2009

  2. Today (1) Put on floor all issues related to TELL1 production- Procurement of components- Manifacturing- Testing (2) Discuss pros/cons of a possible (minor) TELL1 upgrade to decide if/how to proceed (3) Identify possible contributors

  3. Current estimates

  4. General issues Components to be secured:- Glue cards (INFN Genova, difficult to replicate): buy from LHCb- Clock components: TTCrx: buy non rad-hard batch QPLL: OK Special quartzes: possible issue- Fibre connectors:- CCPC:- FPGAs: somewhat old- Memories: soldered- Gigabit ethernet: Manifacturing:- Connectronics (got a quotation comparable to LHCb)- CAEN (contacts ongoing)- Other ? Testing:

  5. Upgrade? • NA62 has 8 TELL1 (different versions) available • TELL1 production to be handled within NA62 • Design is somewhat dated • Take advantage of new production to implement (minor) changes • Strike balance between improvements and exploitation of man-hours in existing design • Cost increase • Delay due to prototyping and testing

  6. FPGA upgrade PP-FPGA SL-FPGA FPGA usage with present “naive” firmware (no DDR memory controller, no trigger processing, no inter-board communication)Limitation on number of pages (→ trigger latency) from internal memory in PP-FPGA for page hit counters

  7. FPGA upgrade Stratix I (2001) considered “mature” product, not recommended by ALTERAMax pin-compatible upgrade is Stratix I 40K (from 25K)No pin-compatible solution with newer familiesEach family requires different power Ongoing discussion w. ALTERA for contribution

  8. Memory upgrade 96MB per PP-FPGA (384MB total)Soldered on board Suggestion by Guido: use standard DDRs on SODIMM (cheaper, standard)Vertical space is not an issue Size (FPGA interface) ?

  9. Practical issues Securing of components New TELL1 schematics, who? when? New PCB layout @ CERN (3-4 weeks estimate) Prototype production (spring 2010?) Testing Production (two batches? testing?)

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